Electronics > FPGA

DDR3 Refresh and Micron DDR3 model

<< < (3/3)


--- Quote from: ddr_controller on January 24, 2023, 04:48:55 pm ---I know that there are multiple ways of refreshing, RAS# based, CAS# (CBR)... But I can't find the description of how each of them works. In my mind, I just imagine that the REFRESH command just refreshes all the banks and that if you want to target specific lines you just open and close that line, but then you have to keep track of the time to know the next refresh.

--- End quote ---

The refresh command just refreshes 1 row group (only a few rows can be refreshed at once) in all the banks simultaneously out of 8192 row groups which each bank has.
Internally in the DDR3, every time you send a refresh that row counter increases by 1.

See block diagram figure 5 on page 16 of the Micron data sheet.  You will see the block 'refresh counter' which has 13 bits, hence 8192 possible refresh address positions.  (Note that the other 2 block diagrams has the refresh counter at 16 bits.  I'm not sure what is going on here.  The slower refresh time for the larger ram chips may just be internally incrementing this counter during the longer refresh period to make up for more rows.)


[0] Message Index

[*] Previous page

There was an error while thanking
Go to full version
Powered by SMFPacks Advanced Attachments Uploader Mod