Electronics > FPGA

Design cascaded sinc filters, how to?

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greenstrike:
Hi guys, I have a doubt about designing cascaded sinc filters: I read I sinc filter is created using a CIC filter.
I've seen, in a decimation filter IC placed behind a sigma-delta modulator, I can use cascaded sinc filters to select desired decimation factor.

Taking a look to CIC filters I need to use following register width:

Register width = Input value register widt + ceiling(sinc order * log2(decimation factor)

I start with 1 bit input value (modulator output), then a 5th order sinc filter, decimation factor by 8.
So 1 + 5*3 = 16 bit

Following sinc filter is a 4th order, decimation factor by 2:
16+4*1=20
..and so on, but taking care of following sinc filters (different orders, different decimation factors), I get up to 85 bits, while ADC output is 24 bit wide.

What's wrong? Do I really work using 85 bit wide registers?
Thanks.

dietert1:
I'd guess you forgot to clip the filter result to some meaningful length after each filter stage. Your first stage filter calculation may require 16 bit yet the result has 3 significant bits as the decimation factor is 8.

Regards, Dieter

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