Disciplined signal clock to PPS

[greenstrike]

Hi to all!

I need help about this:
I need signal clock (1.024 MHz) and sync to supply array of 1-channel ADCs.
I need sync signal aligned to clock so I thought a simple 1:1024 clock divider.
I am using a 32 MHz TCXO, FPGA PLL (I get 128 MHz clock), 1:125 clock divider (I get 1.024 MHz), then second clock divider 1:1024 to get 1 kHz sync signal.
I need to lock 1.024 kHz to 1 Hz PPS signal from GPS receiver, I thought to lock clock signal trimming 1:125 divider, but resolution is too poor for my purpose.
Any ideas?
I also supposed to use VCTCXO instead simple TCXO... but still having poor resolution.
Thanks.

[fourfathom]

You should look at the various GPSDO design topics here.

How much jitter and drift can you tolerate in your clock outputs? 

Yes, modifying your 1:125 division to be 1:124/125/126 will be much too coarse for good PLL operation, but instead of a 1:125 divider you can use a NCO (Numerically Controlled Oscillator) type of divider, or a fractional divider to give you much better average resolution.  You still will have 1/32MHz jitter (31.25 ns), so if that's too much you will need to go to a VCTCXO, or if your FPGA contains a PLL you can multiply that 32MHz up to a higher frequency and run the variable divider from that.

It gets more complicated if your TCXO wander/drift/jitter is excessive.  The 1 PPS tracking loop can only handle so much.
You may not need VCTCXO if your TXCO drift rate is slow enough to allow reasonable

[hamster_nz]

I've successfully used the fine phase shift feature of the Xilinx MMCM to modify the frequency of an onboard XO to track a GPS PPS.

The fine phase shift has 56 steps per cycle of the MMCM's VCO frequency - so around a 20ps step if the VCO frequency is 900MHz. This is far better than can be achieved by mucking around with SERDES or GTYs.

You can adjust 1 shift every dozen or so cycles of the controlling clock. So with your design running with a VCO frequency of 900MHz, and the logic at 100MHz you can shift 8.3M times per second, enough to move the output frequency up to +/-145kHz.

If this is of interest to you I can help out with the design for you. It's pretty simple

- A saturating counter counts in the output clock domain

- the counter gets written to a FIFO when the PPS is seen  (but only if it is a sensible value e.g. +/- 1% of nominal frequency).

- In the 'raw' clock domain, it reads the FIFO and updates the error value

- The 'error' in the count is used to adjust the number and direction of fine phase shifts per second.

- A DDR register outputs the trimmed clock

- It's locked when the error term is sufficiently low for a few cycles.

Just remember to enable the fine phase shift on the MMCM output of interest - you'll most probably need to use a MMCM primitive for this.

[BrianHG]

Either use a TI CDCE913 (or variant) VCXO crystal PLL clock synthesizer to make your FPGA clock.

Tie the 1 PPS GPS to an FPGA input.

Use 2 FPGA outputs to drive a 2N3904/2N3906 to generate a 3 state tuning output voltage to drive the vctrl input of the clock synthesizer.

You FPGA code driving the 2 transistor IOs should only worry if the input GPS 1PPS is ahead of the VCXO output divided down to 1 Hz, drive the 2N3906 on, if it is behind, tune the 2N3904 on, otherwise leave both transistors off to let your charge pump cap hot the tuning speed.

For the 'CDCE913' solution, you can also use a DAC control, or, the 'CDCE913' has an internal I2C controlled DAC tied to it's vctrl pin getting rid of the 2N3904/2N3906 analog solution.


The other choice is to make an FPGA PLL clock set to an exact (1,024,000hz x 512) = 524,288,000 hz by any crystal and PLL settings necessary.

Now, make your divide by 512 clock from the 524.288 MHz (the MSB of this counter is your 1.024MHz sample clock) reset at every rising edge of your GPS 1PPS input.  This will have an occasional +1 or -1 clock adjustment at the 524.88MHz range, (2ns glitch) but your sample clock will be locked onto you external GPS source.

I have done this with Altera and Cyclone IV also using a DDR input and DDR output to achieve better than 1ns glitch.

Also, instead of resetting the divide by 512 counter, you may phase compare and tune the FPGAs PLL's phase control offering 1/64 or 1/16 steps shrinking that 1ns or 2ns correction step down to the ~100ps or ~20ps size.

[greenstrike]

Ok, thanks for suggestions.
I am evaluating digital PLL in verilog, NCO and so on, also VCTCXO with extarnal DAC and PWD driving....
I also found verilog code of what I am looking for (more or less), but now I need to understand how module works:
https://github.com/MorrisMA/1PPS-DPLL

[nctnico]

Also make sure the 1PPS from the GPS receiver isn't wandering around. It is not uncommon for the 1PPS output to wander around +/-50ns so you'd need to filter that as well. A good approach is to lock the FPGA's clock to the 10MHz coming from the GPS receiver by using a DAC + VCTXCO (at least, a voltage controlled overnized oscillator is even better). From there you can start measuring the phase offset between the internal 1PPS and external 1PPS and use a fast / slow filter approach to perform locking and then slow tracking. If the 1PPS from the GPS receiver is wandering around, the slow tracking time constant can be in the ballpark of several minutes.

What really matter is: what level of time synchronisation is required? With a GPS receiver you can get to ballpark +/-50ns between the various nodes. If you need better, then you'll need to look at alternative methods.

[Evan.Cornell]

You could use something like ZL30159. I've used this chip before for this purpose. Not cheap, but it works.