ICE40up pll with external clock howto ?

[darkvador]

I'm struggling with an ice40up5k board (icesugar/icebreaker) to use a pll with the source clock from pin 35
on the icesugar the external clock 12Mhz is connected to pin 35 but each time I want to use the pll with this clock
I get an error...

I tried to read lattice documentation (I'm using Radiant) but I've not found anything clear
is there an example someone explaining clearly how to use the PLL with pin 35 as source clock ?
or someone able to explain how to do that ?

I'm developping an interface to convert a commodore 8032 video signal to a vga signal...
when I try to use the 48Mhz clock, there is too much jitter to have a stable image....

I checked some example given by muse lab tech... but on one example they say it's not working
on the other example it's not using a real pll

thanks

[mon2]

Hi. Personally working with the ICE40UL1K devices on ICECUBE2 toolchain but perhaps the following may help:

https://github.com/icebreaker-fpga/icebreaker-examples/blob/master/pll_uart/pll_uart_mirror.v

https://github.com/lawrie/verilog_examples/blob/master/fpga4fun/pongbreaker/pong.v

[darkvador]

I tried to adapt my code from the pong example

Code: [Select]

    pll0 : SB_PLL40_PAD generic map (FEEDBACK_PATH -> "SIMPLE",
             DIVR => "0000",         -- DIVR =  0
          -- DIVF => "1010011",      -- DIVF =  83
             DIVF => "0111000",      -- DIVF =  83
             DIVQ => "101",          -- DIVQ =  5
             FILTER_RANGE => "001")  -- FILTER_RANGE = 1
        port map (RESETB     => '1',
                  BYPASS     => '0',
                  PACKAGEPIN => clock,
                                  PLLOUTCORE => vga_clock);

but I get this error:

Code: [Select]

Warning-1034: Found non-unate timing arc, from pin "in3" to pin "lcout" of instance "GB_BUFFER_clock_c_g_THRU_LUT4_0_LC_16", in the clock network. Converting the timing arc to positive-unate
I2108: 0 SB_IO_I3C instances present in the design. 2 I3C IOs available in the device
E2694: PLL: pll0.vga_pll_inst could not be placed
E2693: PLL placement is infeasible for the design
I2723: placment information file is dumped at : D:/didier/Developments/lattice/icecube2/vgax/vgax_Implmnt\sbt\outputs\placer\vgax.pcf
I2709: Tool unable to complete IOPlacement for the design
E2055: Error while doing placement of the design
I'm using icecube2 I'm doing something wrong but I don't know what

previously I worked with quartus prime lite and  a DE 10 Lite and never had this type of problems....
the ice40up5k nice, cheap and  powerful but I find lattice documentation a hell

thanks for your help


I tried Icecube2 and radiant... and block on the same problem
I'm not using icestorm simply because I program in vhdl and not verilog...

[darkvador]

I found a solution with Lattice Radiant
I was using the pin35 12Mhz clock for 2 uses the pll and a counter...
when I started using the pin 35 clock only for the pll it worked...

but for icecube 2 it's not working
I get the following error:

@E: FX732 :"d:\didier\developments\lattice\icecube2\vgax\vgax.vhd":46:8:46:11|PLL input clock connected to PACKAGEPIN; must be driven only by input buffer.

I have no idea to solve this problem

[woofy]

Sounds like the internal routing will take the clock to the PLL or the global clock net, but not both.
Try either deriving the counter clock from the PLL output or wire the 12MHz clock to a separate GB pin.

[darkvador]

thanks for your help, it now works with radiant and Icecube
for Icecube I miseed one of the reference to the 12Mhz clock
when I removed it it worked

thanks to all