Xilinx/AMD Artix-7 Memory and FIFO Verilog Models

[trossin]

After experimenting around with the Memory and FIFO generator, I've created some base models of the RAM/ROM and synchronous/asynchronous FIFOs.  I created parameterized models that can be instantiated to create different configurations that can then be simulated using an external simulator from the Vivado environment.  I use Icarus for a simulator and my VcdView program to look at waves (GtkWave works as well).  I see a 10x to 20x speed up in my edit/debug cycle over Vivado.  Also, I don't have to re-run the simulation when adding more signals since I just use value change dumps.

You can find the models, examples and documentation here:

https://sites.google.com/site/tedrossin/home/electronics/xilinxamd-fpga

The models and docs are under Common and the the examples are under Block RAM and FIFO Experiments.  The Experiments have Vivado 2024.1 projects and source as well as test benches that run with Icarus or Vivado.  I also include a little project that uses the serial port or some buttons to control LEDs using PWM.  The words in the Basics section give some info on how to deal with the projects.

I attached the PDF of instructions on how to use and create the models for a project.