Electronics > FPGA

Are GreenPack SPLDs logic prone to glitches?

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This is the official answer I got from Renesas. If I understand them correctly, they say to use synchronous design.

"Digital has the competition and risk, refer to your design, used the same CLK to trigger the internal states, and the CLK be generated by the falling edge of SCLK_IN, will help to avoid these"



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