Does the transceiver link rate affect your modules?

[LoveLaika]

This might be a redundant question, but seeing as I'm doing this for the first time, I wanted to ask. I'm trying to learn how to use an SFP+ transceiver to send/receive data, and I've been looking at Xilinx's Aurora 8b10b wizards to get started. Going through the user guide was very helpful, and I managed to get something working in simulation (using their frame generators/checkers to send data, I've managed to incorporate my own wrapper code to make the aurora interface clearer to use along with my own reset controlling modules and such).

After running tests, I decided to see what kind of speeds my transceiver can support. And then, there in the datasheet, I saw that my transceiver supports a minimum bit rate of ~9.9 Gbps (going up to ~10.3 Gbps) roughly speaking. So far, with the Aurora 8b10b module, I was using it at a link rate of 3.125 Gbps. Looking at the wizard and user guide, Aurora 8b10b only supports up to 6.6 Gbps. If the transceiver can't handle that low of a bit rate to work properly, then that's an issue.

On a whim, I had a look at Aurora 64b66b, and it supports higher bit rates. So, I'm in the process of trying to incorporate it at 10 Gbps, fast enough for my transceiver to use. My question from all this is: does the transceiver's min/max link rate affect what modules I can use (in this case, the link rate specs make 8b10b out of the question), or can it be overcome? Are there any other important factors that I should take into consideration when working with an FPGA and a transceiver? It's not a necessity to use 8b10b; it was the first thing that I was recommended to use when doing data transmission via a transceiver.

(As a side note, I didn't go with the 7 Series FPGA Transceiver Wizard because it was rather confusing trying to understand how it works. I found the Aurora wizards and user guides to be much easier to follow and incorporate. Plus, Aurora examples utilized VHDL whereas the 7-series Transceiver Wizard had everything in Verilog. It's not impossible, but it is kind of a pain to understand.)

[asmi]

The link will only work with the speed of the lowest-speed component - your FPGA transceivers, your SFP+ module, SFP+ module of the link partner, or whatever receiving side IC is (FPGA, ASIC, whatever). Some SFP+ modules will only work at set speeds (see their datasheets), others will work at any speed UP TO the max speed they can handle. So you basically need to configure all parts of this data path to work at the same line rate, encoding, framing and protocol in order to achieve successful communications.

As for 7 series, your goal will determine if you need to know low-level ins and outs of transceivers. It's good to know these in any case (you wouldn't be asking these questions here if you'd read the docs), but if your goal is to utilize some pre-designed IP blocks, you can get away knowing next to nothing about them (for example, you can implement a PCI Express Root Complex by using Xilinx-provided free IP and their Linux driver knowing next to nothing about transceivers, PCIE or IP). I highly recommend anyone getting into multi-gigabit serial links to begin by reading the book "High-Speed Serial IO Made Simple". It's written by Xilinx and is a bit dated, but it's still very good at explaining basic concepts of serial links like clock recovery, framing, encoding, K-symbols, etc. You will not regret studying it for sure!