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Driving an LVDS LCD

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Miti:
I'm trying to make this LCD module do something and the datasheet is a bit confusing ... to me.
First time I look at LVDS LCD and I don't understand how the sync works and why the pixel clock is shifted relative to the LVDS data. Is there any documentation I can read? Is there a verilog code example I can play with?

Miti

asmi:
What FPGA are you using? For Xilinx 7 series check out xapp585 application note.

Miti:
I have two dev boards with Altera Cyclone II and Cyclone IV.

asmi:

--- Quote from: Miti on April 02, 2021, 02:19:21 am ---I have two dev boards with Altera Cyclone II and Cyclone IV.

--- End quote ---
Then maybe some of our resident Altera lovers would pitch in on specifics of IO part.

But basically the "clock" is not really a clock, as it's used for framing (so that receiver can find boundaries of a single transmission). If you look closely, not only it's shifted, but it's also non-symmetrical length-wise (it's high for 4 bit periods, but low for only 3), so that if you sample that clock every bit period, you will get a sequence 1100011. So when receiver tries to lock onto the data stream, it basically bitslips the reception by 1 bit time until it can see that sequence on a clock line - and that's how it knows that it's now properly aligned to the boundaries and so it can start processing data from the data lines knowing they are framed properly. Check the diagram in attachment - I think it shows it more clearly.

The easiest way to implement it is by using 7:1 SERDES modules - one for a "clock" line (which transmits a fixed pattern of 1100011 or 1100001 depending on a panel), and then one more SERDES module for each of data lines. I don't know if Altera supports such mode, so this part you will have to find out yourself, or wait to see if anyone familiar with Altera devices would pitch in.

Also you might want to brush up on your Google-fu. This standard is quite popular even nowadays, so I'm fairly certain you will be able to find some info on this subject on the Internet.

BrianHG:

--- Quote from: Miti on April 02, 2021, 01:49:47 am ---I'm trying to make this LCD module do something and the datasheet is a bit confusing ... to me.
First time I look at LVDS LCD and I don't understand how the sync works and why the pixel clock is shifted relative to the LVDS data. Is there any documentation I can read? Is there a verilog code example I can play with?

Miti

--- End quote ---
I do not like that datasheet's illustration.  So, take a look at page 13 at the bottom.  See that they 'Recommended transmitter: DS90C383 (Texas Instruments) or equivalent'.  I would first go to TI's DS90C383 data sheet and see how they output their data.

For Altera, you will end up using the 'altlvds_tx' function set the 4 channels and the appropriate number of bits/channel.
TI illustrations are dead simple and properly explained.  You would have to set the altlvds_tx to 7 bits.  The CLK out channel will be a fixed 7'b1100011' number while you video and embedded sync will be on the other 3 channels.  (Note that channel TD isn't used as your chosen panel is only 18bit color.)

Modelsim will have no trouble showing you what your code is outputting when testing.

When assigning the output pins, you will need to set them to LVDS (higher speed, but fewer choice of IOs on FPGA), or, LVDS_E_3R (more flexible choice of almost all IOs on FPGA) outputs.

(holy shit, they scrambled up the bit positions....)

Or, if you can find a dev board with a similar LCD already on it, download their example CD and use their code.

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