Ok, so here's my ALTLVDS_TX module and I think I got it right because I see exactly what I expect at the outputs. Now I would need a video controller and a pattern generator. I think I would need the tx_outclock for that, I was thinking that the falling edge would increment the H and V counters, and the rising edge would load the tx_in register. However, if you look at the phase of that clock relative to the first bit on one LVDS output, the rising edge comes after the data needs to be valid. What's the technique here? The phase shift of the tx_outclock relative to tx_out doesn't do it, I can't do negative phase shift.
I'm having a little difficulty following your logic, or train of thought.
Internally in the FPGA, everything should be at 1x clock, IE, 1 pixel clock, always rising edge, all video generator counter and image processors working at that 1x clock.
You should be outputting the 18bit color data, 3 bit HS,VS,DE, (we are at 21 bits), plus the 7 bit clock pattern (we are at 28 bits) into the altlvds_tx singular 28bit parallel input. The altlvds_tx should take that data with pixel clock, in internally generate it's own PLL accelerating the 28bit parallel pixel clock speed input to a serial output stream of 4 lanes by 7x clock speed serial output.
You should never have to worry about the when to increments the HS/VS on weird clock phases.
Note that the altlvds can be setup to be clocked on the incoming data with the tx_inclock so you may ignore or disable the tx_outclock. The tx_outclock is at the same speed as the tx_inclock, just taken after the PLL generated by the altlvds_tx. If your design is very high FMAX and you need to run a serializer with a >250MHZ parallel
input with GHz outputs, using this output as your logic design's system clock,
not an output pin, helps improve fabric routing and FMAX limitations. You are running your parallel input at ~50MHz, so you don't need to use it.
Do not look at the phase difference on the scope. The tx_outclock was not meant to be outputted, it is used to internally clock the logic input and it will appear as a weird phase compared to the output data as you are looking at the clock for the input gates, not the time from when that clock runs until the serial shift register output the data.
Now, if you have having a pin-pin timing skew on the 4 bit output pins, this is a different problem where there are a few solutions to fix.
Also, remember that the altlvds_tx will shift out the 7 bits from right to left...