Easy Quartus II / Cyclone III Question

[NorthernWing]

So I currently have the displeasure of learning how to use Quartus II 13.0 to implement a design on an old Cyclone III chip.  My god this is awful.  Yeah it's a 14 year old FPGA, but it's what I've got and frankly this EP3C16 still has more capacity and is faster than most of the modern chips I can get my hands on right now anyway.

I usually write my hierarchy as ["device.vhd"] -> ["top.vhd"] -> [Fabric/Logic], where top is the top level of the RTL/logic itself, and device instantiates chip-specific hardware like PLLs, IO buffers, etc.

I've got synthesis, p&r, timing, and simulation all completing successfully in Quartus II here, but I can't for the life of me find any documentation, libraries, or menu options for instantiating hard macros like the I/O buffers and PLL/clock conditioning.  I know they exist because the thing has an EMIF and misc PLL cores/etc, but where exactly are these described?

[oPossum]

Tools menu, Megawizard Plug-In Manager.

If you can't find something where it should be, check the I/O category. They like to hide stuff there.

[NorthernWing]

Ah yep, that's it - looks a lot like the Vivado IP catalog.  Much appreciated, not sure how I missed that one.

Time to see if I can turn a pair of LVDS buffers into a SAR ADC on this thing.