FPGA DSP filter to convert 16bit words to 10bit words at higher sample rate

[InterestedTom]

I am currently targeting the iCE40HX8K series of FPGAs using nMigen and I want to design a filter to upsample and truncate 16bit words at >100MHz from an SDRAM to 10 bit words at up to 240MHz.

No DSP blocks inside, but I was thinking I could use BlockRAM based constant coefficient multipliers.

I could probably just work through the books I have and start trying to design/implement something but I think it would be helpful to discuss this with someone with more experience in this area.

I am keen to stick to python3 and probably scipy.signal as the filter design toolbox, I have access to matlab, but I want to make my design and methodology more accessible to hobbyists.

Any useful advice, please feel free to respond!

[gregben]

Forgive my naivete, but how is this different than just writing the 10 MSBs into a 10 bit wide register at the SDRAM read rate and reading it at the output of the register at 240 MHz? The 6 LSBs are simply no-connects.

[SiliconWizard]

Forgive my naivete, but how is this different than just writing the 10 MSBs into a 10 bit wide register at the SDRAM read rate and reading it at the output of the register at 240 MHz? The 6 LSBs are simply no-connects.

Upsampling requires proper filtering to be half usable. But of course we don't know anything about the context here.

And for the OP, I'm sorry, but I'm not sure I really understood the requirements to begin with. You start with 16-bit samples? What's the original sample rate? Why do you want to upsample?

Regarding nMigen, I have absolutely no experience with this. But if you want to design a typical upsampling filter that can put out samples @240MHz on a iCE40HX, it will need to be done with a pretty long pipeline IMO. You'll need to figure out if the resulting latency is acceptable in your context.

But knowing a bit more about what you really want to achieve may help suggesting alternatives.

[gnuarm]

I am currently targeting the iCE40HX8K series of FPGAs using nMigen and I want to design a filter to upsample and truncate 16bit words at >100MHz from an SDRAM to 10 bit words at up to 240MHz.

No DSP blocks inside, but I was thinking I could use BlockRAM based constant coefficient multipliers.

I could probably just work through the books I have and start trying to design/implement something but I think it would be helpful to discuss this with someone with more experience in this area.

I am keen to stick to python3 and probably scipy.signal as the filter design toolbox, I have access to matlab, but I want to make my design and methodology more accessible to hobbyists.

Any useful advice, please feel free to respond!

What you need is a multirate interpolation-decimation filter.  You want to upconvert, so an interpolation filter.  But the ratio is not an integer, so you need to combine an up conversion with a decimation so an interpolation-decimation filter.   This will be a huge amount of calculation without some optimization which would make it a multirate filter. 

The process is interpolation to increase the sample rate, filtering to remove the artifacts and finally decimation to obtain the final sample rate.  Because of the inserted samples being zeros, this can be greatly optimized. 

To get a rate of 2.4 you would need to interpolate by 12 and then decimate by 5.  To interpolate by 12, 11 zero samples are inserted between the 100 MSPS samples creating a 1200 MSPS stream.  This 1200 MSPS stream needs to be filtered to remove the artifacts of the zero insertions.  This would be a very difficult filter to implement because of the high speed.  But we don't need to calculate products for the zero samples which makes it more like the 100 MSPS filter even if that is still a lot of calculations. 

A similar process is used to decimate to 240 MSPS, you only need to throw out samples.  Again, this can be accommodated in the filter by simply not calculating the output samples you don't need further reducing the computations.  This is a bit hard to view in your mind if you are not familiar with it.  There are many good references on the web for it including illustrations.

To effectively remove the artifacts from zeros insertion you will need a reasonably long FIR filter... so lots of calculations even after eliminating the unneeded calcs.

The part that worries me is the spec of the data stream as >100 MSPS.  This number needs to be well defined and a rational ratio to the output rate.  If the ratio of sample rates is not defined by two small integers, this may be a problem.

[InterestedTom]

The reason I put >100MHz is I hadn't firmed up on exact data rate for the SDRAM since that's not a straightforward datasheet spec if I remember correctly.

I've actually forgotten which project this was for though... I think it might have been some vector graphics thing using a DAC targeted at VGA output.

[gnuarm]

The clock rate on the SDRAM data sheet is provided as a max.  You can use any frequency below that.  That doesn't change the problem much unless you get it to an exact integer multiple of your sample rate, then the problem is just an interpolation filter without the complication of a decimation filter. 

I'm not entirely sure I understand all the details, but that's ok, it's not my project.