Author Topic: ECP5: Setting Vref off recomended limits. Any experiences?  (Read 1697 times)

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Offline bsccaraTopic starter

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ECP5: Setting Vref off recomended limits. Any experiences?
« on: January 07, 2025, 07:45:31 pm »
On a design I'm doing with a ECP5U I'm planning to have a bank of IO set as SSTL18 to use as inputs for LVCMOS signals between 1.2V and 3.3V. For that I'll need to set the external Vref up to 1.65V, which is outside the recomended range. According to the datasheet on table 3.1 the maximum voltage on any IO pin is 3.63V, which includes the pins used for routing the Vref into the FPGA, while the recomended Vref range stated on table 3.2 is 0.5V to 1.0V, but with a note that states:

Quote
1. For correct operation, all supplies except Vref must be held in their valid operation range. This is true independent of feature usage.

Also, table 3.12 states that the maximum Vih for SSTL18 is 3.465V. To me it seems that it should be safe to do but I'm not sure if a voltage over 1.0V on Vref or a voltage difference on the inputs over 0.9V will overload the input comparators in the IO pads and degrade their AC response. Has anyone tried this or has any opinion on the matter ?
 


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