Hi. Would anyone here have experience in using the Efinix T4 F49 WLCSP packaged FPGA ?
If yes, specifically, how to deploy the SPI Active x1 Mode to boot using an external SPI flash? This package does not offer JTAG pins so a pre-flashed device must be present to load the IP into the CRAM.
Respectively, for us to flash the IP onto a blank PCB, do we hold CRESET_N line LOW and then we can use an external SPI bus master to flash the IP onto the external memory device? The (AN006) Trion FPGA memory guide is not clear to us and would rather avoid using a mux onboard to steer the SPI lines in the external programmer or FPGA direction.
The T4 FPGA appears to be ~$.60 USD on LCSC.com which is very attractive for us to consider as a CPLD replacement.
To rephrase, how do we park this FPGA in the 49 ball WLCSP package into a tri-state mode so that we can use the external SPI flash programmer without conflict on the shared pins.
Thanks.