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Hi ej
yeah same with mpsoc etc /axi/amb connectors.
anyway, so far, so good with Efinix.

WHat can it do for me ? Well currently I seek to deal with the heat. it costs fancy metalwork to deal with the heat,  and the completed Efinix design *will likely *  be lower power, according to power estimator. about half !   
Still, what you pay for with Xilinx is the absolute benchmark  superb quality of the documentation, tools and logicores. Unbeatable.  (disclaimer I am a Xilinx alliance partner) 
Efinix device are low comparative cost, and the tool chain is improving quite quickly. and they seem to listen. 

It will take me a little while to go to being efficient and effective with high level language design which I will need on the Efinix. Fortunately, gates are cheap.  How is it for getting timing closure on a external 64 lane wide 1200 Msps LVDS bus, I dunno yet.

I used to use Microblaze alot. Then I got used to having an A53 core (admittidly running down at 600 megs) and 16 bits of DDR4 attached (600 meg clock) for an otherwise 2 Mbyte requirement.... and being rather haphazard with code efficiency, rooms for giant deug buffers, whole of program updating, etc (I use FreeRTOS+TCP) and having the neon cores if I wanted them- IE that much horsepower in hand gives me upgrade proof capability.  At a heat and complexity cost. The MPSoC is a complex beast- not to be underestimated whatever your skill.

Technique on the efinix will be more high level synthesised cores, and custom instructions on the 200 meg Sapphire RISC-V and  32 MB of HyperRAM.  (200 megs is about what it will do with complex configuration)  .

My feeling is that I am abotu a year ahead from where I really want the Efinix toolchain to be in terms of performance/stability. But if you dont use it and dont push them, it will not advance...


--- Quote from: glenenglish on November 25, 2022, 08:53:40 pm ---yes get onto factory support. If you have difficulty finding the right people I know someone.

--- End quote ---

Thanks to Harald at Efinix (Europe) for help on this one. He suggested updating to the latest patch (3.17) which has some improvements in this area.

He also mentioned that the jitter depends on VCO speed, so I tried reconfiguring the PLL to run the VCO as fast as possible.

It's *much* better now  ;D


--- Quote from: AndyC_772 on November 28, 2022, 03:36:13 pm ---He also mentioned that the jitter depends on VCO speed, so I tried reconfiguring the PLL to run the VCO as fast as possible.
--- End quote ---
Pretty standard across all FPGA vendors.

did you see NOV27 another patch out

*** 2022.1.226.3.# patch notes
    -- [Trion] Addresses functionality issues with PLL phase-shifted output
       clocks and post divider = 1 PLL setting [PT-1695, PT-1207, SIP-264, DOC-1019, DOC-1026]
    -- [Trion] Significantly increases F_VCO, F_PFD maximum frequencies for Trion PLLs (not
       including T4, T8F49 & T8F81 devices) [PT-1695, DOC-1026]   
    -- [Titanium] Use classic router (same as used in Efinity 2021.2) by default
    -- [Titanium] Fixes small number of cases where global clocks incorrectly routed
       edge destinations [VPR-1716]
    -- [Titanium] Fixes instantiation of DSP48 with different MODE values [SYN-632]
    -- [Titanium] Fixes functionality issue in certain DSP cascaded cases [SIP-252]
    -- Fixes issue where IP Manager mistakenly deletes Sapphire standalone applications
       folder upon Sapphire IP regeneration [IPM-425]
    -- Fixes jtag_bridge read flash error on MX25L device [PROG-417]
    -- Fixes issue with programmer's JTAG clock speed control [PROG-411]

Yes, that's v2022. Seems my support enquiry was timely...!


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