Enpirion/altera switching regulator problems

[motocoder]

Anyone here have any experience with Enpirion (now Altera) switch mode regulators? We are using a number of them to generate the power supply rails for a board with an FPGA and DRAM on it. One of them an ER2120QI used to generate the 2.5v rail, is occasionally not coming up.

When it fails, it will either not come up at all, or come up well below the target voltage, or do other weird things like generate a sawtooth waveform on the PG (Power Good) pin!

I have no experience with these parts (wasn't my choice to use them), so am hoping someone here can shed some light or offer some theories.

Thanks

[PeteH]

I've used the embedded inductor variants of this part.

 Your exact usage would be needed to diagnose this. What inductor are you using? What is the expected 2.5v current/inrush? What is the total capacitance on this rail?

Add all DDR2 termination currents?

Are you capacitively loading the PG pin? Open drain outputs shouldn't have a triangle wave.... Unless of course, AVINO is in OC or slewing down. Do you have the right decoupling on AVINO and the filter to AVIN?

[motocoder]

I've used the embedded inductor variants of this part.

 Your exact usage would be needed to diagnose this. What inductor are you using? What is the expected 2.5v current/inrush? What is the total capacitance on this rail?

Add all DDR2 termination currents?

Are you capacitively loading the PG pin? Open drain outputs shouldn't have a triangle wave.... Unless of course, AVINO is in OC or slewing down. Do you have the right decoupling on AVINO and the filter to AVIN?

Hi PeteH -

• The inductor is 3.3 uH, part number PCMC063T-3R3MN
• This rail is expected to source about 1.7A.
• Total capacitance on this rail is approximately 40uF (4 x 10uF in parallel).
• This rail is not related to DDR. It is one of the power rails for the FPGA.
• We are not capacitively loading the PG pin. Note that most of the time, this circuit is working,and PG is putting out a nice output that goes high with the expected rise time. It's only when it goes into this failed state on start-up, and even then it's rare that PG is emitting this strange sawtooth wave.
• AVINO has a 4.7uF cap to ground
• AVINO is connected through a 10 ohm resistor to AVIN. The AVIN net also has a 1uF cap to ground, is connected to the M/S pin, and is pulling up (via a 10K resistor) the PG output.

I should also add that these component values were reviewed / suggested by an engineer at Enpirion.

[motocoder]

Oh, I also want to add that this is the EVT version of the board, and it's very possible there is some problem there, for example something leading to an over-current condition on this rail. I'm just hoping someone with experience with this part can point to some likely root cause for me to follow up on investigation.

I went back and looked at some oscilloscope captures that the board assembler sent. They did measure the current out of this thing. Based on the waveform I think they tapped into the circuit on the inductor (which goes from the SW output of the chip to the filter caps on the output). In a normal start-up cycle, peak current is 540mA, but during the failed startup cycle - the one with the funky sawtooth waveform on PG- there is a very brief spike of current to 2.78A, with corresponding output voltage of 560mV, before the output voltage and current drop back to zero.

[David Hess]

From your description, I would suspect current limiting or fold-back current limiting is causing the problem.  The later can lead to the regulator "latching" on or off.

[motocoder]

From your description, I would suspect current limiting or fold-back current limiting is causing the problem.  The later can lead to the regulator "latching" on or off.

Yes, it certainly looks like there was over-current and the regulator protection circuit cut the output. I have no idea what might be causing that though, as most of the time the board starts up and everything is fine - no overcurrent, no issues with the 2.5V rail...

[David Hess]

From your description, I would suspect current limiting or fold-back current limiting is causing the problem.  The later can lead to the regulator "latching" on or off.

Yes, it certainly looks like there was over-current and the regulator protection circuit cut the output. I have no idea what might be causing that though, as most of the time the board starts up and everything is fine - no overcurrent, no issues with the 2.5V rail...

That is where fold-back current limiting can cause problems.  Even with loads that the regulator could normally power, it is possible for the regulator to latch itself off because the current limit drops when the output voltage drops.

The ER2120QI datasheet does not say anything about fold-back current limiting being used though so there is some other problem.  Maybe poor decoupling or layout is causing false triggering of the current limit or other abnormal operation.  This is supported by the presence of a low and incorrect output voltage as well as the behavior of the power good signal.

The ER2120QI datasheet is pretty poor.  I would have expected more practical application information.

[PeteH]

Random OC events.... Are you following rail sequencing recommendations for this FPGA? Is this a xilinx part?

Are your io rails coming up after your 2.5v rail? What about the core rail?

[PeteH]

Read about the oc action in the datasheet. If the EN pin is pulling low, then the controller is acting on successive peak limit current events, a counter inside is used to provide a small amount of glitch immunity.

[PeteH]

Triangle wave on pg is likely just the capacitive decay of AVINO LDO due to the EN fault overrides. It would coincide with an integer multiple of the SS period.

[motocoder]

Random OC events.... Are you following rail sequencing recommendations for this FPGA? Is this a xilinx part?

Are your io rails coming up after your 2.5v rail? What about the core rail?

It's an Altera part. Yes, we are following rail sequencing recommendations for the FPGA - at least the design is such that we expect that is the case. This done by tying the PG signal from an upstream regulator to the EN signal of a downstream regulator (along with a pull-up resistor). The sequence is one we've used before on this same part, and was reviewed by Altera.

Now, that said, I can't say for sure that some glitch is not triggering a regulator to start up out of sequence. I did check yesterday the rail in the sequence after the 2.5V rail (it's a 1.05V) to make sure that it isn't starting up out of sequence. I was looking into this because I can see a small glitch on the PG output of the 2.5V regulator when the 12V source supply comes online. Everything looked good there, however, even during a failed cycle of 2.5V.

Also, in case it's relevant, the 12V input to the board goes through a slew rate limiter before it fans out to the various regulators.

[motocoder]

Triangle wave on pg is likely just the capacitive decay of AVINO LDO due to the EN fault overrides. It would coincide with an integer multiple of the SS period.

I think let's forget about the triangle (sawtooth actually) waveform on PG. I reviewed my notes, and I see now this was only after the vendor removed the FPGA from the board.

[motocoder]

Another data point:

When observing a failed cycle, the voltage sometimes gets to around 1.0V before sharply dropping back down (as if over-current protection in the regulator dropped the output voltage). During some good cycles, however, you can observe a step in the ramp-up around this voltage. I.e. the voltage seems to increase like an RC circuit charging to 1.0V, and then take off in what looks like a normal ramp-up to 2.5V. Observing some of the other rails, powered by other Empirion parts, I do not observe this behavior; I just see a steady almost linear ramp-up from 0V to the target voltage.

[motocoder]

Ok, I have attached some scope screen captures from Friday and Saturday. I was testing with different boards on the two days, and the behavior is a little different between them. The file names of the attachments call out which board is which, and I've included a failed start-up cycle and a good start-up cycle for both.

On Saturday (board 2), I was also measuring the 1V05 rail, which is the one after 2V5 in the sequence, to see if it was inadvertently being triggered out of sequence. That's why the traces for board 2 are a different set of signals.  Here is a list of the signals in the scope captures:

As mentioned before, the 2V5 regulator is an ER2120QI. The 1V05 regulator downstream from that is an EN2342QI.

"Good Cycle Board 1 (2V5 only).png" and "Failed Cycle Board 1 (2V5 only).png"

• Ch1 (Yellow): 2V5 rail output of regulator
• Ch2 (Cyan): AVIN into 2V5 regulator. It looks like there may be a small oscillation on this signal, but we measured this with a better scope and did not see this.
• Ch3 (Pink): POK output of 2V5 regulator
• Ch4 (Blue): 12V output of slew rate limiter

"Good Cycle Board 2 (2V5 and 1V05).png" and "Failed Cycle Board 2 (2V5 and 1V05).png"

• Ch1 (Yellow) - 12V PVIN to 2V5 regulator (after slew rate limiter)
• Ch2 (Cyan) - 2V5 rail
• Ch3 (Pink) - PG output of 2V5 regulator / EN input to 1V05 regulator
• Ch4 (Blue) - 1V05 rail

[PeteH]

What's the value of your SS cap?
Looks like a pre-biased startup, maybe a parasitic path to this rail for another (the prestartup hump may be in sync with a previously sequenced supply).

I would maybe try increasing the SS cap if it's small, you usually have up to 50ms for most FPGA rails (ie 200us ~50ms) to get the rails from 0 to nominal. This is almost non-monotonic, some manufacturers will blame this kinked startup....

Is this a stratix V chip?

[motocoder]

What's the value of your SS cap?
Looks like a pre-biased startup, maybe a parasitic path to this rail for another (the prestartup hump may be in sync with a previously sequenced supply).

I would maybe try increasing the SS cap if it's small, you usually have up to 50ms for most FPGA rails (ie 200us ~50ms) to get the rails from 0 to nominal. This is almost non-monotonic, some manufacturers will blame this kinked startup....

Is this a stratix V chip?

SS cap is 68nF. Yes, this is Stratix V.

[motocoder]

I typed that last reply on my phone, and somehow the cap value got deleted. I've corrected it - the cap on SS is 68nF.

[PeteH]

That value shouldn't cause anything too extreme in terms of inrush...

OK, so only Stratix power pin connections on this 2.5V regulator.

Can you list the power pins (by naming convention) that are tied to this regulator?
i.e.:
Stratix V:
Are you bringing up the core (VCC = 0.9V or 0.85V?)
VCCHIP & VCCHSSI - are these tied to the same power supply as VCC?

VCCPD  == 2.5V?
VCCPGM == 2.5V?
VCCA_GXB/GTB == 2.5V?

VCCA_FPLL = 2.5V
VCC_AUX = 2.5V


I am not too familiar with Altera FPGAs, I don't have a feeling for how the different rails behave during power up.

Having a requirement of up to 1.7A required for this regulator and choosing a 2A part, is a little close to the edge, especially if the FPGA is undergoing firmware development / is a newer venture, I've learned from past projects that you should always leave enough margin for full growth in areas of use within the FPGA; I usually assume that the firmware guys will set up the FPGA to maximize current draw (strong IO / better margins) and blow their estimates away with logic use / transceiver speeds / PLLs - sometimes there's a bit of feature creep.

Inrush due to capacitance is only about 1.83mA/uF. I think 40uF for a 1.7A FPGA rail (running at 500kHz or more?) is a little light as well, not sure about the magnitude of on-chip decoupling for the stratixV family...

[motocoder]

That value shouldn't cause anything too extreme in terms of inrush...

OK, so only Stratix power pin connections on this 2.5V regulator.

Can you list the power pins (by naming convention) that are tied to this regulator?
i.e.:
Stratix V:
Are you bringing up the core (VCC = 0.9V or 0.85V?)
VCCHIP & VCCHSSI - are these tied to the same power supply as VCC?

VCCPD  == 2.5V?
VCCPGM == 2.5V?
VCCA_GXB/GTB == 2.5V?

VCCA_FPLL = 2.5V
VCC_AUX = 2.5V


I am not too familiar with Altera FPGAs, I don't have a feeling for how the different rails behave during power up.

Having a requirement of up to 1.7A required for this regulator and choosing a 2A part, is a little close to the edge, especially if the FPGA is undergoing firmware development / is a newer venture, I've learned from past projects that you should always leave enough margin for full growth in areas of use within the FPGA; I usually assume that the firmware guys will set up the FPGA to maximize current draw (strong IO / better margins) and blow their estimates away with logic use / transceiver speeds / PLLs - sometimes there's a bit of feature creep.

Inrush due to capacitance is only about 1.83mA/uF. I think 40uF for a 1.7A FPGA rail (running at 500kHz or more?) is a little light as well, not sure about the magnitude of on-chip decoupling for the stratixV family...

I was mistaken on the total capacitive load. There were a bunch of bypass caps on another page of the schematic that I missed. This rail is also divided into 3 separate nets with a couple of chokes:

2V5 rail -> FPGA VCCIO3/4/7/8, VCCPD3/4/7/8, and also a header for external JTAG programming.
2V5 rail -> choke -> Oscillator
2V5 rail -> choke -> FPGA VCC_AUX1/2/3/4/5/6

If you ignore the chokes and just add up all the capacitor values, it's about 67uF (I said 40uF before).

The core voltage is 0.9V and comes up first in the power cycle (i.e. before this rail).
Looks lke VCCPGM and VCCA_GXB are 3.0V (the regulator before this one in the sequence).

[PeteH]

Is the FPGA configured for Fast or Standard POR? (should be standard)

[motocoder]

Is the FPGA configured for Fast or Standard POR? (should be standard)

Looks like MSEL[4..0] are all tied to ground, so that configuration scheme would be with the fast POR delay.

[motocoder]

Is the FPGA configured for Fast or Standard POR? (should be standard)

Looks like MSEL[4..0] are all tied to ground, so that configuration scheme would be with the fast POR delay.

And by the way, the POR delay is *after* the rails are all up. The fast POR is to keep the total time low so the device can be ready in time to meet some requirements for an external device.

[PeteH]

I agree with you on that point. POR time is from the 'POR trip level' of the last monitored rail to config start.

Can you measure in series with any of the chokes/beads to track down who/which derived net is causing the abnormal current spike? If it's an altera VCC group, it's on them to assist in diagnosing this, especially since the sequencing requirements were followed.

It's weird to see two boards show different prebias levels for this rail, which doesn't seem to affect this glitch.
My inclination would be to 1) increase SS period to see if it changes anything, 2) increase output capacitance if possible.

Increasing the inductor value will help lower the peak-peak current and will slightly improve the maximum output capability.

Technically Altera states that the estimator is accurate for predicting power use, if the FPGA is still in reset, there shouldn't be significant current transients that go way beyond a given logic/fpga use scenario...

[motocoder]

Pete - thanks very much for all your help in troubleshooting this. I think the next step is to determine myself if there actually is an over current, or if it is just the part thinking that due to noise on some other signal. Unfortunately, there may not be a clean place to break the circuit for that other than the inductor, which is really not what I want. I'm going to look into how I can do that today.

BTW, in parallel with my investigation, Enpirion has been looking into it. Based on the timing of events, they believe that the OC detector is triggering and that simultaneously an under voltage detector is triggering. Their theory on the undervoltage is that it's either noise coupled to the FB or SS pin (probably FB).

[motocoder]

Looks like the mystery is solved. There was a net on the PCBGRIP not in the schematic, and most definitely not a good connection. 3 regulators all configured as master had thei SYNC pins tied together.