Electronics > FPGA

Ethernet and FPGAs?

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radiolistener:

--- Quote from: asmi on October 14, 2021, 04:06:05 am ---Actually the most pin-efficient solution is SGMII. But it requires FPGA which can do 1.25Gbps over differential pair. Something like 7 series speed grade 2 or higher. Or slower one, but with gigabit transceiver.

--- End quote ---

for GMII PHY you're needs to be very careful with transmission lines layout and length. For SGMII it will be even more important.

jeremy:

--- Quote from: radiolistener on October 14, 2021, 05:14:39 am ---
--- Quote from: asmi on October 14, 2021, 04:06:05 am ---Actually the most pin-efficient solution is SGMII. But it requires FPGA which can do 1.25Gbps over differential pair. Something like 7 series speed grade 2 or higher. Or slower one, but with gigabit transceiver.

--- End quote ---

for GMII PHY you're needs to be very careful with transmission lines layout and length. For SGMII it will be even more important.

--- End quote ---

SGMII is actually easier than GMII; your only problem is really just routing a single diff pair. And it is only 1.25Gbps, so as long as you use a calculator for the impedance matching, you should be able to make some fairly long traces without much effort.

As for the original post, you don't need to use a full MAC if you just want to get data from FPGA to PC as a starter project and can plug the device straight into the PC, you can just write the raw ethernet frame for a UDP packet straight to the PHY and it will work (though the OS may force you to assign a static IP to the PC).

ejeffrey:

--- Quote from: radiolistener on October 14, 2021, 05:14:39 am ---
--- Quote from: asmi on October 14, 2021, 04:06:05 am ---Actually the most pin-efficient solution is SGMII. But it requires FPGA which can do 1.25Gbps over differential pair. Something like 7 series speed grade 2 or higher. Or slower one, but with gigabit transceiver.

--- End quote ---

for GMII PHY you're needs to be very careful with transmission lines layout and length. For SGMII it will be even more important.

--- End quote ---

Sgmii is actually pretty easy.  There is a single differential pair in each direction and length matching between tx and rx is not critical. Length matching withing the diff pairs is important but not hard to accomplish as they will be routed together from adjacent pins.  You can invert the polarity in the fpga if you need to.

jeremy:
If I recall the tx and rx pair don’t have any length matching requirements at all (between tx and rx, you still need to length match the pairs + and -). More of the issue is ensuring that clocks are stable on both ends with low jitter.

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