How much "Higher level" verilog is used in industry? (Adder example)

[NorthGuy]

On Xilinx 7 series you can make a super-fast 48x48 bit adder using a single DSP tile. AFAIK you can push it into 400+ MHz range if you pipeline it properly.

If you're allowed to pipeline, then all you need to do in a single clock is an 1-bit adder. If you pipeline 48 of these you'll get a 48-bit adder in 48 stages. This will work as fast as the clock can go, certainly faster then DSP. 2-bit adders will go that fast as well. I think even if you pipeline 4-bit adders (12 stages for the 48-bit adder) you still will beat DSP's speed.

If you can't pipeline (because of  some sort of circular dependency, for example) then DSP will be much slower and you probably will be able to beat it with a pure logic adder.

[ehughes]

Designing from raw "gates" is not "low level" and may in fact be worse than just using "+".  FPGAs don't have raw gates.  They have LUTs + Registers, muxes, etc.

If you want to design from a low level, then you can directly instantiate the LUT's, etc.    For example, the Picoblaze is extremely space efficient and directly uses the LUTs and logic in the slices.

https://github.com/ptracton/Picoblaze/blob/master/Picoblaze/kcpsm6.vhd


You *always* start from behavioral code and then optimize from there.   Most of the vendors have a synthesis guide that tell you the best way to infer a particular pattern.