You know those times when you feel like youre on a roll, and everything is working out. Then it stops working out, and all of a sudden you cant even seem to do something simple?
Ive hit a situation like that.
Ive started learning Verilog, and playing around with a MAX V CPLD development board.
First I made an LED blink using a clock divider module I wrote, which worked great.
Then I made a few other modules, some muxes and shift registers, and the simulations/testbenches all said they were working.
Then I got cocky and tried to string a bunch of them together into a larger design based on a discrete version that I have made, which of course
didnt work.
OK, back to basics and lets try to figure out which bit isnt working, so I decided to try and see if my pins were being toggled correctly by a microcontroller by mirroring some internal signals out to another pin and, well, I cant even get a simple buffer from one input pin to one output pin to work now...
This is what I tried:
`timescale 1ns/1ps
module test_top
(
input loop_in,
output reg led1
);
// mux_2_1 ds_data_mux (
// .sel(loop_in),
// .in0(1'b0),
// .in1(1'b1),
// .out(led1)
// );
always @(loop_in) begin
led1 = ~loop_in;
end
endmodule
I also tried led1 as a simple "output" and used an assign to set the value of it to the inverse of loop_in.
The code for the mux, which is one of the modules I wrote and the testbench said was working is:
`timescale 1ns/1ps
module mux_2_1
(
input wire in0,
input wire in1,
input wire sel,
output out
);
assign out = sel ? in1 : in0;
endmodule
Can someone slap me the right way and figure out what is going on?
After all of this I went back to a simple LED blinky with my clock divider and that still works, so theres probably something fundamental that Im not understanding here.
Thanks!