Electronics > FPGA

Fast ADC interface with FPGA

**knight**:

I have to interface a fast ADC with an FPGA and then do the data processing. The FPGA used will be Zynq Ultrascale+ RFSoC ZU29DR. I have been given the information that ADC_clk = 4x FPGA_clk. ADC output data is 12/16-bits. The data processing will be multiply-accumulate over a number of samples.

--- Code: ---I = I + adc_data * cos;

Q = Q + adc_data * sin;

--- End code ---

There is a data sample output at every clock of ADC. So, it will be something like:

--- Code: ---I[0] = I[0] + adc_data[0] * cos[0];

Q[0] = Q[0] + adc_data[0] * sin[0];

I[1] = I[1] + adc_data[1] * cos[1];

Q[1] = Q[1] + adc_data[1] * sin[1];

--- End code ---

And so on.

I have a DDS CORDIC-LUT module that can be instantiated to generate 4 sin, cos values parallelly based on the phase word. What I'm not sure about is how to multiply with adc_data as adc generates faster than what the FPGA can accept.

I have come up with the below timing diagram and architecture. Any input will be appreciated.

**hamster_nz**:

That timing diagram looks a little odd to me - there is eight data values per FPGA clock cycle, not four.

Not sure what the question is (if any), but you will need to use SERDES to separate out the four samples.

See attached diagram for what you need to construct for each bit (the PLL gets shared by all bits).

You will need to get very friendly with:

- the simulator (to check it works before trying in H/W)

- The clocking resources on your FPGA - you have to write your design to map onto the FPGA's dedicated structures. To not do so will result in failure.

- Documentation for the SERDES block on your FPGA - they are simple to use, but have so many options, and it can be tricky to reset them correctly.

The other option is to clock the edge of the design twice as fast, and then use the much simpler DDR registers to capture the data.

This might be of use (even though Ultrascale I/O hardware is different): https://github.com/hamsternz/Artix-7-HDMI-processing/blob/master/src/deserialiser_1_to_10.vhd

**hamster_nz**:

Oh, and if latency isn't an issue you can use the sample input as the initial CORDIC vector, so when you calculate SIN & COS you will actually get X*SIN(phase)*CORDIC_GAIN and X*COS(phase)*CORDIC_GAIN, removing the need for any multipliers.

**knight**:

--- Quote from: hamster_nz on August 16, 2022, 09:45:13 pm ---

--- Quote ---That timing diagram looks a little odd to me - there is eight data values per FPGA clock cycle, not four.

--- End quote ---

That is because we are generating sin, cos pair, hence 8 values per cycle.

--- Quote ---Not sure what the question is (if any), but you will need to use SERDES to separate out the four samples.

--- End quote ---

Unfortunately, I cannot use SERDES. Is there other interface option available?

--- End quote ---

**knight**:

--- Quote from: hamster_nz on August 16, 2022, 09:53:19 pm ---Oh, and if latency isn't an issue you can use the sample input as the initial CORDIC vector, so when you calculate SIN & COS you will actually get X*SIN(phase)*CORDIC_GAIN and X*COS(phase)*CORDIC_GAIN, removing the need for any multipliers.

--- End quote ---

Sounds good :-+

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