Electronics > FPGA

Faster FPGA compilation times using... FPGA? GPU?

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Hey all,

just out of curiosity really, because I couldn't find any information online, not could Chat GPT when I asked them...  :)

With increasing FPGA project sizes synthesis, fitting and routing take longer and longer. I usually run a compile in a simulator first, only because on a Cyclone V Quartus takes about 2 minutes before it gets to the first syntax error. Also, Windows Quartus GUI is terribly slow compared to a command line Linux build.

Nevertheless, it got me thinking, would it be possible to accelerate the whole build process using an additional FPGA PCI card (or even over Ethernet just for kicks), that returns a binary file? Would it be possible using a PC's GPU for example?

My first thought was, yes, but probably nobody does it because all processes are proprietary. But then I remembered there are a few projects that can do Open Source Xilinx Series 7 and other brands. So why not?

Is it maybe because the synthesis and routing processes are more iterative in nature than a calculation? No idea.

If you guys have clues or know about such a project, I'd be interested in knowing.



The main issue with any 3rd party FPGA software, is that producing a functional, guaranteed reliable binary for any FPGA requires a timing model of the device. That model specifies all the best and worst case delays through the part across all possible variations of temperature, supply voltage and part-to-part variability.

Only the device's manufacturer knows all this information.

A 3rd party binary might work on one particular device just fine but fail on another part, or it might work when it's cold but not hot, or vice versa. If the problem is setup time, slowing the clock might help, but you'll never know what the maximum guaranteed speed would be. If it's a hold time violation, no change in clock rate will ever make it work reliably.

FPGA code is *nothing* like a set of instructions which have defined, guaranteed meaning, and can be easily shown to be correct or incorrect. Timing is *everything*.

Advocates of 3rd party FPGA tools don't address this critical issue, and until an FPGA vendor decides to release the complete, guaranteed timing model for a family of parts, it's just not possible to produce a guaranteed reliable binary - whether it's produced using a CPU, or a GPU, or an abacus.

I would like to see such an accelerated tool that generates binary for a typical room temperature, nominal part scenario for development purposes. I can quickly make a bugfix, compile and run a test on live data (e.g. specific video data).
Once I am happy, I can run a nightly build with a regular synthesis tool for a customer release.

Looks like a job for quantum computing.


--- Quote from: betocool on September 25, 2023, 01:01:32 pm ---Cyclone V Quartus takes about 2 minutes before it gets to the first syntax error.

--- End quote ---

Unless your code base is millions of lines, I don't see how can it possibly take more than a second to find all syntax errors.

It is slow because it's bloated, not because it has to be slow. Same goes for Xilinx's Vivado. Nothing you can do about it unless you can write your own.


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