Author Topic: First FPGA project. Looking for advice  (Read 5669 times)

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Offline hermitengineerTopic starter

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First FPGA project. Looking for advice
« on: May 14, 2021, 03:50:10 am »
This is my first time designing for an FPGA, and learning Verilog from zero.  So I'd appreciate any constructive criticism on coding, style, etc.  I developed the code in Vivado and simulated and synthesized it for an XC7S6 series chip to verify that it acts as it is supposed to.  It works (virtually) but uses maybe 5% of the chip's resources.

Second, this is a project to duplicate the functionality of a 40-pin DIP designed in the late 70's by General Instruments for an ancient game system.  As such, the board should also be about 40-pin DIP sized.  So, I'd also appreciate suggestions for an FPGA to use, along with the level shifters, voltage regulator(s), and flash memory.  Obviously, size would be the biggest issue.

Thanks
 

Offline asmi

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Re: First FPGA project. Looking for advice
« Reply #1 on: May 14, 2021, 04:50:36 am »
You might want to take a look at Digilent's CMOD boards: CMOD A7 or CMOD S7. They have DIP-48 size, so not sure if it's going to be OK.

If you want to design your own, making it so small is going to be a challenge. The smallest package for S7 is 8x8 mm, but it's 0.5 mm ball pitch, so you will need to use advanced PCB tech. If you prefer to use more conventional tech, you can take a look at A7's CPG236/238 package (it's 0.5 mm pitch too, but the pinout is such that it's possible to route it using conventional PCB process) - it's 10x10 mm. The smallest "conventional PCB-friendly" S7 package is CSGA225, but at 13x13 mm it's probably a tad too close to the your size limits (assuming 0.7 inch or 17.8 mm for the PCB width). It could be doable though.

I think the XC7A12T-1CPG238 or XC7A15T-1CPG236 would be the best choice because they are the smallest accessible with conventional PCB tech. I've attached pinout diagrams and package drawing for A15T option for your convenience (taken from UG475), A12T has the same physical dimensions and footprint, but different pinout (see aforementioned user guide UG475 for all these details).

Online up8051

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Re: First FPGA project. Looking for advice
« Reply #2 on: May 14, 2021, 09:02:40 am »
It looks that your project is simple, maybe CPLD circuits will be enough.
For example: ATF150x 5V supply, PLCC44
 

Offline woofy

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Re: First FPGA project. Looking for advice
« Reply #3 on: May 14, 2021, 10:06:49 am »
I did something similar for the Intel 4004 CPU, except I never needed the level shifting as it was a 3.3v replica from the start. But it did fit on a 16 pin DIP footprint. I used the Lattice ice40LP1k and GD25Q20C flash for that.
TheCP16xx (A PDP11 inspired device) is more complex so I would choose the ice40HX8k. The CB132 package will fit the 40 pin DIP footprint. A suitable flash could be the AT25SF081. Bidirectional 3.3v-5v level shifting could be done with TXS0108E devices. This will not take much power so linear regulators will be fine. You can ignore the 12v and -3v and just power from the 5v supply.

 

Offline emece67

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Re: First FPGA project. Looking for advice
« Reply #4 on: May 14, 2021, 03:36:20 pm »
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« Last Edit: August 19, 2022, 04:24:43 pm by emece67 »
 

Offline Bassman59

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Re: First FPGA project. Looking for advice
« Reply #5 on: May 14, 2021, 06:19:45 pm »
This is my first time designing for an FPGA, and learning Verilog from zero.  So I'd appreciate any constructive criticism on coding, style, etc. 

How much experience do you have doing synchronous digital logic design?
 

Offline hermitengineerTopic starter

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Re: First FPGA project. Looking for advice
« Reply #6 on: May 14, 2021, 08:06:57 pm »
Your code mixes synchronous, asynchronous and clock (usages of) signals in a, more or less, liberal way. For example, in CARADDR.sv, signals BUSAK & INTAK are asynchronous, P2 is a clock and SR3 is used: asynchronously (for card_load_count); synchronously (for LD); and as a clock (for ADDR). Also, P2 is sometimes active on the rising edge, other times on the falling one. There's a block (at least, CARADDR.sv) with two asynchronous inputs (BUSAK & SR3 on the first always). I think all these is not exactly kosher now, although maybe it was back in the '70s, when using 74/4000 ICs.

Yeah I was working with the timing diagrams of the CP1600 CPU which is used by the system, an internal document detailing the behavior of the original chip, and the results of actual observation of its behavior.  It's an ... interesting setup.  As I think I mentioned in the code, the CPU is a 4-state machine where P2 rise is TS1, P2 fall is TS2, second rise is TS3, and second fall is TS4.  The fun part is that this is the processor's state machine, and outside of the processor we would need some fuzzy logic to figure out which state it is in, if that is even necessary.  In the case of this chip, it does not seem to be, as long as you are okay with the fact that P2 has 2 positive edges for the same bus operation.

So, for instance, the write to memory does not have valid data on the first pulse but does on the second.  With the current code, the memory is written on both positive edges, but the correct value wins.

Anyway, what I do know is that the 3 control lines should be valid on the rising edge of P2 and throughout the high level.



This chip is a split-brained one, where the first half is mainly clocked by P2 and the other half is mainly clocked by SR3.  SR3 is a level trigger for the purpose of enabling the SD outputs, but its edges also trigger a couple of internal changes.  Rationale for the count:  The graphics chip will ask the CPU for control of the bus (BUSRQ) early in an attempt to ensure that the CPU has time to honor the request before the graphics chip needs it.  But that means it might still be in the middle of displaying that last line when the CPU relents.  At that time, BUSAK will be active but loading of values should not begin yet.  So there is the activation counter which is reset by SR3's pulses, ensuring that the next set of values do not begin to load until that line is finished.  So the count should be reset by the edge of SR3, at least.  But holding reset asynchronously is also an option.  Maybe even the preference because the edges are about 8 clocks apart.

Similarly, the DTB condition is pretty much a level trigger for enabling DB as an output.  The bus expects to see the value through both P2 pulses (in other words, 3 phase changes) while DTB is active, so once we are sure there is a DTB that we are supposed to respond to, we have to hold it until the condition changes.


There are register w/o any means to initialize them asynchronously (albeit for some people, or in some scenarios, this may not be an issue).
Yeah this chip will be running constantly because it's part of the video display system.  The 20-position shift register represents the background tiles for every 16 lines (8 lines per tile, but doubled because of the TV's interlace).  The graphics chip that works along with this chip initiates the load sequence of the background tiles from its internal memory, 20 at a time, then repeats those 20 for the next 7 lines, then makes it load the next 20, and so on, until it has filled the screen.  Then the graphics chip sends an interrupt request to the CPU which responds with an INTAK.  We see the INTAK and reset the address while entering CPU mode.

Anyway, because of that, it should only take 1 cycle to get everything into a known state, so it would likely not be noticeable.  That is probably why the original designer didn't add a reset pin, even though the other chips have one.


The next is a matter of taste, but a little of indentation can help to ascertain what is the asynchronous part of a block from the syncronous one:
Code: [Select]
always@(negedge SR3 or posedge INTAK)
begin
    if(INTAK) begin
        ADDR <= 0;
    end else if(LD) begin
        ADDR <= ADDR + 1;
    end
end
vs.
Code: [Select]
always@(posedge INTAK, negedge SR3) begin
  if (INTAK) begin
    ADDR <= 0;
  end else
    if (LD) begin
      ADDR <= ADDR + 1;
    end
end

I can see either argument.  My personal preference (both in general programming and in this) is that if it's a sequence of conditions rather than a hierarchy, I prefer to keep the indenting the same.  One could argue that it IS a hierarchy, and you are technically correct.  But logically, it's just a list of conditions where the first one that's true wins.  It's logically closer to a case statement.  This is probably why some languages added the syntatic sugar of "elseif".



Also, putting the clock (P2) inside if conditions (this happens in the 1st always block of CARADDR.sv) drives one to think that it is not a clock.
I'll have to review my rationale for this block, and consider whether or not it's still valid (may be a leftover from my crash course in Verilog).




This is my first time designing for an FPGA, and learning Verilog from zero.  So I'd appreciate any constructive criticism on coding, style, etc. 

How much experience do you have doing synchronous digital logic design?

I guess this is your way of saying "What a mess of spaghetti code"  :)

Some experience, but definitely not up to modern standards.  I understand edge and level triggering, at least, and I am conscious of propagation delay.

But the device that I'm duplicating was designed before modern design disciplines were established, so some of the odd triggering you might be noticing is unfortunately necessary.
 

Offline hermitengineerTopic starter

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Re: First FPGA project. Looking for advice
« Reply #7 on: May 14, 2021, 10:05:41 pm »
When I started thinking about this project, I did buy an Alchitry AU kit from Sparkfun.  That's why I used Vivado for development--it's a Spartan Artix-7 based board.  Of course learning Vivado was about as much effort as learning Verilog was, and I still can't claim to be an expert in either yet.

But the kit comes with a USB port for programming, which you apparently have to do with their Alchitry software rather than the Xilinx programmer.  It does seem to have a breakout board for the GPIO pins, though I'll have to solder on their provided header plugs.  It also comes with a 3rd board with 4 7-segment displays, 5 buttons, and a large bank of DIP switches.  So at least I have a supposedly working board for experimentation.

I'll look into the other suggestions on this thread though.
« Last Edit: May 14, 2021, 10:08:02 pm by hermitengineer »
 

Offline emece67

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Re: First FPGA project. Looking for advice
« Reply #8 on: May 14, 2021, 11:04:23 pm »
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« Last Edit: August 19, 2022, 04:24:57 pm by emece67 »
 

Offline james_s

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Re: First FPGA project. Looking for advice
« Reply #9 on: May 14, 2021, 11:17:29 pm »
Before you reinvent the wheel, look at existing hardware solutions for FPGA or CPLD replacements of vintage ASICs used in arcade games. It's possible there will be an existing design you can use as-is or with modifications to the pinout. Then you just have to focus on the code. For development purposes you can use just about any dev board. In practice I find that simple resistors on the input lines is adequate for level shifting, and the 3.3V outputs will drive 5V TTL stuff just fine. If it were life safety hardware I'd say definitely go with proper level shifters but for a game? Probably not really necessary.
 

Offline hermitengineerTopic starter

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Re: First FPGA project. Looking for advice
« Reply #10 on: May 15, 2021, 04:02:46 am »
Verilog is somewhat clumsy when differentiating the asynch and clocked parts of a block. In VHDL you put the CLK inside an if condition, but in the forms "CLK'event and CLK = '1'" or "rising_edge(CLK)", that clearly expose CLK as a clock. But Verilog does not have this mechanism and it may be difficult to tell what is, or not, a clock. The usual idiom in Verilog is that the clock is in the sensitivity list of the always (with a pos/negedge) *AND* it is not "used" inside the block. Other signals in the sensitivity list and used inside are supposed to be asynchronous inputs to the block, and signals not in the sensitivity list are synchronous. Thus my prior comment about P2 inside an if.

Oh, I see.  It's expected that every comparison at the top level reference a named event?  So the code ought to look something like:
Code: [Select]
always@(negedge SR3 or posedge INTAK)
begin
    if(INTAK) begin
        ADDR <= 0;
    end else if(!SR3) begin
        if(LD)
            ADDR <= ADDR + 1;
        end
    end
end

So that means the reference to !LD in the previous always block should also be within a sub-block since it is not an event?
 

Offline hermitengineerTopic starter

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Re: First FPGA project. Looking for advice
« Reply #11 on: May 15, 2021, 04:50:38 am »
Before you reinvent the wheel, look at existing hardware solutions for FPGA or CPLD replacements of vintage ASICs used in arcade games. It's possible there will be an existing design you can use as-is or with modifications to the pinout. Then you just have to focus on the code. For development purposes you can use just about any dev board. In practice I find that simple resistors on the input lines is adequate for level shifting, and the 3.3V outputs will drive 5V TTL stuff just fine. If it were life safety hardware I'd say definitely go with proper level shifters but for a game? Probably not really necessary.
Awwww come on, let me have my fun.

Well, I did do a search for an FPGA implementation of this chip, at least.  There's a core of the entire system for the MiSTer written in VHDL (with a much larger SytemVerilog/VHDL/TCL glue that I guess interfaces it with the core of the platform), but it combines all 4 of the chips that do graphics into a single entity and integrates them too tightly to be separated without basically reimplementing the one I want.
 

Offline james_s

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Re: First FPGA project. Looking for advice
« Reply #12 on: May 15, 2021, 06:11:30 am »
Awwww come on, let me have my fun.

Well, I did do a search for an FPGA implementation of this chip, at least.  There's a core of the entire system for the MiSTer written in VHDL (with a much larger SytemVerilog/VHDL/TCL glue that I guess interfaces it with the core of the platform), but it combines all 4 of the chips that do graphics into a single entity and integrates them too tightly to be separated without basically reimplementing the one I want.

I'm not trying to stop you from having fun, I'm just pointing out that there are existing devices that have a CPLD or FPGA on a carrier board meant to plug into a DIP socket, and given the highly flexible nature of CPLD and FPGA pins, you might not have to make many if any changes to an existing hardware design to make it work. Either way the main challenge is in writing and debugging the HDL to make it do what you want it to do. If the design is small enough to fit into a CPLD that's going to be easier in most cases than an FPGA. FPGAs offer cool features like clock PLLs and hardware multipliers but they typically require external configuration memory and multiple power supply rails.
 

Offline hermitengineerTopic starter

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Re: First FPGA project. Looking for advice
« Reply #13 on: May 15, 2021, 09:05:01 am »
I'm not trying to stop you from having fun, I'm just pointing out that there are existing devices that have a CPLD or FPGA on a carrier board meant to plug into a DIP socket, and given the highly flexible nature of CPLD and FPGA pins, you might not have to make many if any changes to an existing hardware design to make it work. Either way the main challenge is in writing and debugging the HDL to make it do what you want it to do. If the design is small enough to fit into a CPLD that's going to be easier in most cases than an FPGA. FPGAs offer cool features like clock PLLs and hardware multipliers but they typically require external configuration memory and multiple power supply rails.
Oh you mean other 40-pin FPGA/CPLD projects.  I understood you to mean repeating someone else's RA-3-9600.  Yeah you're right.  That would also be worth looking into.

Are there CPLDs that have RAM?  I do have a simple CPLD dev kit, but of course it only has a few dozen combinatorial logic gates with various choices of output.  This particular chip has 352 16-bit words of RAM, as well as 20 14-bit registers arranged as a circular shift register.  I suppose it may also be possible to add an external RAM chip or two, if they can fit on a DIP-sized board with the CPLD.

Edit:  Just looked around and found a 128Kx16 SRAM for about $1.5, and it can come in a BGA or TSSOP44 package, both of which could fit on a DIP40.  That would likely allow the logic to fit within a CPLD (though it needs another 16+9+xx pins for the memory interface).  But that is a workable alternative.
« Last Edit: May 15, 2021, 10:00:39 am by hermitengineer »
 

Offline emece67

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Re: First FPGA project. Looking for advice
« Reply #14 on: May 15, 2021, 09:43:16 am »
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« Last Edit: August 19, 2022, 04:25:12 pm by emece67 »
 

Offline emece67

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Re: First FPGA project. Looking for advice
« Reply #15 on: May 15, 2021, 10:39:27 am »
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« Last Edit: August 19, 2022, 04:25:30 pm by emece67 »
 

Offline NorthGuy

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Re: First FPGA project. Looking for advice
« Reply #16 on: May 15, 2021, 03:40:34 pm »
As now we do not have control about what the synthesizer and P&R tools are doing ...

You still can directly instantiate LUTs, add routing delays perhaps, and thereby make combinatorial logic glitch-free. The only problem is that the tools will not do this for you, so you're on your own. Your idea with fast clock is much easier to implement.
 

Offline hermitengineerTopic starter

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Re: First FPGA project. Looking for advice
« Reply #17 on: May 15, 2021, 06:23:07 pm »
A problem when using so many asynchronous signals is that glitches on them can trigger unexpected behaviors. Back in the day, the topic of logic hazards was taught at universities, that also taught techniques to avoid them (mainly based on adding redundant terms in the logic functions). As now we do not have control about what the synthesizer and P&R tools are doing, old techniques are no longer applicable and the current technique of synchronous design replaced them, and the old methods were somewhat forgotten (universities here seem not to taught it anymore, is that common elsewhere?)

I see.  Yeah I made every effort to design the circuit so that the combinatorial changes were finalized before the triggers that used their values.  For instance, in "DMA mode", the internal memory always has the data at the current address output-enabled.  On positive edge of SR3, this data is latched into the shift register, and on negative edge of SR3, the address is incremented.  Therefore the data is always valid when latched.  As far as presenting this data to the SD side, there is a timing window for how long SD is allowed to be in flux after SR3 goes positive.  The FPGA, at least, ought to make that window easily.  The data output may initially be the previous contents of the shift register, but the memory load should happen and propagate well before the other chips on that bus begin to examine it.

The one asynchronous signal that I am most concerned about, false "DTB" signal, is somewhat mitigated by the fact that between bus operations, the CPU always drops all control lines to 0 for a CPU cycle before initiating the next state.  DTB is both BC1 and BC2 high, so the only way to reach this state by accident is from the situation where BDIR is also high (INTAK) and BDIR drops first.  However, the CPU had control of the bus for the INTAK but had already high-z'd the bus by the time the false DTB would cause this chip to burp data to the DB bus for those brief nanoseconds, and only if it had been addressed by the INTAK.
 

Offline james_s

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Re: First FPGA project. Looking for advice
« Reply #18 on: May 15, 2021, 10:24:16 pm »
Are there CPLDs that have RAM?  I do have a simple CPLD dev kit, but of course it only has a few dozen combinatorial logic gates with various choices of output.  This particular chip has 352 16-bit words of RAM, as well as 20 14-bit registers arranged as a circular shift register.  I suppose it may also be possible to add an external RAM chip or two, if they can fit on a DIP-sized board with the CPLD.

Edit:  Just looked around and found a 128Kx16 SRAM for about $1.5, and it can come in a BGA or TSSOP44 package, both of which could fit on a DIP40.  That would likely allow the logic to fit within a CPLD (though it needs another 16+9+xx pins for the memory interface).  But that is a workable alternative.

To my knowledge, no, if you need RAM that either means FPGA or external RAM chip. Which of these options makes sense depends, it could be a tossup between them.

Either way I would focus on getting the HDL working first and then figure out what hardware you want to build for the final device. I have a DE2 dev board that I use for this sort of thing, it has lots of IO, SRAM and DRAM onboard, a bunch of switches, some buttons and LEDs and 7 segment displays that are handy for monitoring things during development.
 

Offline hermitengineerTopic starter

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Re: First FPGA project. Looking for advice
« Reply #19 on: May 16, 2021, 05:59:36 am »
Okay, I've attempted to implement some of the criticism about coding.  In the process, I also discovered a value that was being sampled at the same time it was being changed  :palm:

But in taking a close look at the synthesized and implemented schematics, I was drawn to the fact that it optimized out DB[14] output to always be ground.  WTF?  The sim code depends on all 16 bits working correctly.  Then I looked around some more and realized that the internal memory is only storing the 15th bit.  Again, WTF?  I guess I should make sure:  How do you assign to an entire 16 bits at a time?

The current code:
always@(negedge P2) begin
    if(db_to_ram)
    begin
        memory[ram_addr] <= DB;
    end
end

where memory is defined as:
reg [15:0]  memory [351:0];

and DB is defined as:
inout wire [15:0] DB

The assignment at least worked for the RTL elaboration and for the simulation, but the synthesis only assigned the 15th bit, and the implementation step agreed.
 

Offline miken

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Re: First FPGA project. Looking for advice
« Reply #20 on: May 16, 2021, 07:10:02 am »
Ah, the joys of bringing up a new design ;) Take a look at the synthesis warnings and I think you'll understand eventually what is happening. Remember that the tools prune whatever isn't actually being used.
 

Offline hermitengineerTopic starter

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Re: First FPGA project. Looking for advice
« Reply #21 on: May 16, 2021, 08:27:13 am »
Ah, the joys of bringing up a new design ;) Take a look at the synthesis warnings and I think you'll understand eventually what is happening. Remember that the tools prune whatever isn't actually being used.
This may be a Vivado question, but where do I find these warnings?  I have a "Messages" tab with 2 warnings listed, both in the "General" subtree.  One is that the IP directory cannot be found (so what?  I'm not using any IP) and the other is that the GeneratedRun file is not found (?)

In the synthesis message tree, no warnings or errors.  In the synthesized design message tree, no warnings or errors.
 

Offline asmi

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Re: First FPGA project. Looking for advice
« Reply #22 on: May 16, 2021, 01:58:53 pm »
This may be a Vivado question, but where do I find these warnings?  I have a "Messages" tab with 2 warnings listed, both in the "General" subtree.  One is that the IP directory cannot be found (so what?  I'm not using any IP) and the other is that the GeneratedRun file is not found (?)

In the synthesis message tree, no warnings or errors.  In the synthesized design message tree, no warnings or errors.
Look in synthesis and implementation logs. They are in the "Log" tab on the bottom of the Vivado window.

Also remember that the goal of FPGA is to OUTPUT stuff. So if synthesis or implementation can mathematically prove something does not affect output, it's going to be pruned. For example, if you only write to the memory but never read, this whole part is going to be removed. If you do read back memory, but only certain bits affect output, all other bits will be optimized away.

You can prevent stuff from being optimized away by using attributes (like "KEEP"), but I strongly advise against it unless you know what are you doing.

Offline rstofer

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Re: First FPGA project. Looking for advice
« Reply #23 on: May 16, 2021, 04:29:10 pm »
Look in the Message folder (tab) on the Console pane after running Synthesis.  It is unlikely that your code isn't generating a bunch of warnings.
Under RTL Analysis, Open Elaborated Design, open the Schematic and see what logic has been generated.  This will require successful synthesis.
Sampling and signal change do not occur simultaneously on the clock edge.  The signal is sampled no closer than tsetup before the clock and the output is stable no sooner than thold after the clock.  That's why asynchronous logic is so hard to create.  All of the potential transitions have to be covered in the Karnaugh Map and these small undefined regions generate glitches.  We get around this problem by designing synchronous logic.

https://www.nandland.com/articles/setup-and-hold-time-in-an-fpga.html

« Last Edit: May 16, 2021, 04:49:05 pm by rstofer »
 

Offline hermitengineerTopic starter

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Re: First FPGA project. Looking for advice
« Reply #24 on: May 16, 2021, 07:53:45 pm »
Here's the log.  It seems to be the same thing as the messages, just in pure text format.  But it explicitly says "0 warnings, 0 errors".  Maybe the warnings I need are disabled by default and there's a setting to turn them on?

Code: [Select]

*** Running vivado
    with args -log RA_3_9600.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source RA_3_9600.tcl



****** Vivado v2020.2 (64-bit)
  **** SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
  **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source RA_3_9600.tcl -notrace
Command: synth_design -top RA_3_9600 -part xc7s6cpga196-2
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7s6'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7s6'
INFO: [Device 21-403] Loading part xc7s6cpga196-2
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 8220
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1017.004 ; gain = 0.000
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'RA_3_9600' [C:/Users/Documents/RA_3_9600/RA_3_9600.srcs/sources_1/imports/new/RA-3-9600.sv:21]
INFO: [Synth 8-6157] synthesizing module 'RINGBUFFER' [C:/Users/Documents/RA_3_9600/RA_3_9600.srcs/sources_1/imports/new/RINGBUFFER.sv:30]
INFO: [Synth 8-6155] done synthesizing module 'RINGBUFFER' (1#1) [C:/Users/Documents/RA_3_9600/RA_3_9600.srcs/sources_1/imports/new/RINGBUFFER.sv:30]
INFO: [Synth 8-6157] synthesizing module 'CPUADDRDECODER' [C:/Users/Documents/RA_3_9600/RA_3_9600.srcs/sources_1/imports/new/CPUADDRDECODER.sv:26]
INFO: [Synth 8-6155] done synthesizing module 'CPUADDRDECODER' (2#1) [C:/Users/Documents/RA_3_9600/RA_3_9600.srcs/sources_1/imports/new/CPUADDRDECODER.sv:26]
INFO: [Synth 8-6157] synthesizing module 'CPUBUSDECODER' [C:/Users/Documents/RA_3_9600/RA_3_9600.srcs/sources_1/imports/new/CPUBUSDECODER.sv:23]
INFO: [Synth 8-6155] done synthesizing module 'CPUBUSDECODER' (3#1) [C:/Users/Documents/RA_3_9600/RA_3_9600.srcs/sources_1/imports/new/CPUBUSDECODER.sv:23]
INFO: [Synth 8-6157] synthesizing module 'CARDADDR' [C:/Users/Documents/RA_3_9600/RA_3_9600.srcs/sources_1/imports/new/CARDADDR.sv:23]
INFO: [Synth 8-6155] done synthesizing module 'CARDADDR' (4#1) [C:/Users/Documents/RA_3_9600/RA_3_9600.srcs/sources_1/imports/new/CARDADDR.sv:23]
INFO: [Synth 8-6155] done synthesizing module 'RA_3_9600' (5#1) [C:/Users/Documents/RA_3_9600/RA_3_9600.srcs/sources_1/imports/new/RA-3-9600.sv:21]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1017.004 ; gain = 0.000
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
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---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1017.004 ; gain = 0.000
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1017.004 ; gain = 0.000
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1017.004 ; gain = 0.000
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [C:/Users/Documents/RA_3_9600/RA_3_9600.srcs/constrs_1/imports/new/RA_Pins.xdc]
Finished Parsing XDC File [C:/Users/Documents/RA_3_9600/RA_3_9600.srcs/constrs_1/imports/new/RA_Pins.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/Documents/RA_3_9600/RA_3_9600.srcs/constrs_1/imports/new/RA_Pins.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/RA_3_9600_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/RA_3_9600_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1037.844 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1037.844 ; gain = 0.000
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1037.844 ; gain = 20.840
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7s6cpga196-2
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1037.844 ; gain = 20.840
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1037.844 ; gain = 20.840
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1037.844 ; gain = 20.840
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
   2 Input    8 Bit       Adders := 1     
   2 Input    4 Bit       Adders := 1     
+---Registers :
               16 Bit    Registers := 1     
               14 Bit    Registers := 20   
                8 Bit    Registers := 1     
                3 Bit    Registers := 1     
                1 Bit    Registers := 3     
+---Muxes :
   2 Input   16 Bit        Muxes := 2     
   2 Input   14 Bit        Muxes := 2     
   2 Input    9 Bit        Muxes := 1     
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 10 (col length:20)
BRAMs: 10 (col length: RAMB18 20 RAMB36 10)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
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Start Cross Boundary and Area Optimization
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---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1037.844 ; gain = 20.840
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

Distributed RAM: Preliminary Mapping Report (see note below)
+------------+------------+-----------+----------------------+---------------------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives                |
+------------+------------+-----------+----------------------+---------------------------+
|RA_3_9600   | memory_reg | Implied   | 512 x 16             | RAM64X1D x 6 RAM64M x 30 |
+------------+------------+-----------+----------------------+---------------------------+

Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1037.844 ; gain = 20.840
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
Inferred a: "set_disable_timing -from a -to z i_12(tricell)"
Inferred a: "set_disable_timing -from a -to z i_13(tricell)"
Inferred a: "set_disable_timing -from a -to z i_9(tricell)"
Inferred a: "set_disable_timing -from a -to z i_10(tricell)"
Inferred a: "set_disable_timing -from a -to z i_11(tricell)"
Inferred a: "set_disable_timing -from a -to z i_6(tricell)"
Inferred a: "set_disable_timing -from a -to z i_7(tricell)"
Inferred a: "set_disable_timing -from a -to z i_8(tricell)"
Inferred a: "set_disable_timing -from a -to z i_3(tricell)"
Inferred a: "set_disable_timing -from a -to z i_4(tricell)"
Inferred a: "set_disable_timing -from a -to z i_5(tricell)"
Inferred a: "set_disable_timing -from a -to z i_0(tricell)"
Inferred a: "set_disable_timing -from a -to z i_1(tricell)"
Inferred a: "set_disable_timing -from a -to z i_2(tricell)"
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1037.844 ; gain = 20.840
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

Distributed RAM: Final Mapping Report
+------------+------------+-----------+----------------------+---------------------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives                |
+------------+------------+-----------+----------------------+---------------------------+
|RA_3_9600   | memory_reg | Implied   | 512 x 16             | RAM64X1D x 6 RAM64M x 30 |
+------------+------------+-----------+----------------------+---------------------------+

---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1037.844 ; gain = 20.840
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 1037.844 ; gain = 20.840
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 1037.844 ; gain = 20.840
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 1037.844 ; gain = 20.840
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 1037.844 ; gain = 20.840
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 1037.844 ; gain = 20.840
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 1037.844 ; gain = 20.840
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

Static Shift Register Report:
+------------+--------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|Module Name | RTL Name           | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E |
+------------+--------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|RA_3_9600   | rb/RING_reg[0][13] | 19     | 14    | NO           | NO                 | YES               | 0      | 14      |
+------------+--------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+

---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage:
+------+---------+------+
|      |Cell     |Count |
+------+---------+------+
|1     |BUFG     |     2|
|2     |LUT1     |     6|
|3     |LUT2     |    32|
|4     |LUT3     |    26|
|5     |LUT4     |    11|
|6     |LUT5     |     5|
|7     |LUT6     |     6|
|8     |RAM64X1D |     6|
|9     |SRLC32E  |    14|
|10    |FDCE     |    12|
|11    |FDPE     |     2|
|12    |FDRE     |    44|
|13    |IBUF     |     6|
|14    |IOBUF    |    30|
+------+---------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 1037.844 ; gain = 20.840
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:20 . Memory (MB): peak = 1037.844 ; gain = 0.000
Synthesis Optimization Complete : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 1037.844 ; gain = 20.840
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1037.844 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 36 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1044.445 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 36 instances were transformed.
  IOBUF => IOBUF (IBUF, OBUFT): 30 instances
  RAM64X1D => RAM64X1D (RAMD64E(x2)): 6 instances

INFO: [Common 17-83] Releasing license: Synthesis
25 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 1044.445 ; gain = 27.441
INFO: [Common 17-1381] The checkpoint 'C:/Users/Documents/RA_3_9600/RA_3_9600.runs/synth_1/RA_3_9600.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file RA_3_9600_utilization_synth.rpt -pb RA_3_9600_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Sun May 16 13:41:20 2021...
 


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