Electronics > FPGA

FMEA of a digital design

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matrixofdynamism:
I have carried out FMEA of physical circuits long ago where we have failure modes like resistor become open circuit or short circuit or its value drifts e.t.c and use MIL standard document to caculate the failure probability for different components on a circuit board.

At this time I need to carry out FMEA on a digital design that has been created in RTL and shall be implemented in ASIC. It is the design itself that needs to go through FMEA or FMEDA (don't know if they are the same thing or not). There is basically no resource on the internet on how to do this, i.e define failure modes for an RTL design. How can one proceed with this exercise?

Someone:
Hello SEU:
https://en.wikipedia.org/wiki/Single-event_upset

AK6DN:
And TMR:
https://en.wikipedia.org/wiki/Triple_modular_redundancy

And FMEA:
https://en.wikipedia.org/wiki/Failure_mode_and_effects_analysis

Tation:
Please, note that this info may be outdated:

* look for (digital) fault modeling, mainly the stuck-at fault model
* look for LSSD https://www.slideshare.net/PraveenKumar3664/level-sensitive-scan-designlssd-and-boundry-scanbsDesign tools can compute, from post P&R simulations, the fault coverage of your design (% of faults that can be detected by the test vectors, not to be confused with the code coverage). You must design the vectors (and a way to apply them in a real chip, LSSD comes here) to achieve ~100 % fault coverage. There are also tools helping on these (look for ATPG).

Foundries may reject design + vectors combos showing too low a fault coverage, as they may use your vectors to test the chips before cutting/packaging/shipment.

If your design does have some kind of redundancy (like TMR above), you will be far from 100 % fault coverage, but talking with the foundry explaining it may help. Or you may need a mechanism to disable redundancy during tests.

Your best source of info will be your CAD tool manuals and foundry interface.

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