The point is indeed that a real open drain would allow a 3.3V Vcc chip to speak to a 5V slave without internal diodes or drivers being fried, for instance.
This is *not* the case with an emulated open-drain behaviour of a classic push/pull tristate I/O without the push. Current will then flow, possibly through internal clamping diodes and do funny things, depending on the I/O architecture.
WRT schmitt triggers: You can safely forget about these with an up to date FPGA, as their standard I/O hysteresis and slew rate configuration options are way more than sufficient, and you typically do the debouncing yourself by sampling the SCL input with an internal clock of a multiple of the max. standard SCL frequency. Most FPGA types allow you to configure a slow slew rate/glitch filtering option in their I/O constraints files and tools mostly detect if you are emulating an open drain output.
For standard applications, I'm clocking in 4 SCL bits and check for "1100" for a falling edge condition - good enough to detect glitches as well. Clock streching support may require another setup, but you don't seem to require that.