FPGA Benchmarking algorithms

[steamedhams]

What are these Bench marking algorithms that I keep seeing in academic papers??

Stuff like "apex2"

[cfbsoftware]

According to https://docs.verilogtorouting.org/en/latest/vtr/benchmarks/ apex2 is one of the "MCNC20" benchmarks

"The MCNC benchmarks [Yan91] are a set of small and old (circa 1991) benchmarks. They consist primarily of logic (i.e. LUTs) with few registers and no hard blocks.

Warning: The MCNC20 benchmarks are not recommended for modern FPGA CAD and architecture research. Their small size and design style (e.g. few registers, no hard blocks) make them unrepresentative of modern FPGA usage. This can lead to misleading CAD and/or architecture conclusions."

The reference to [Yan91] is:

"S. Yang. Logic Synthesis and Optimization Benchmarks User Guide 3.0. Technical Report, MCNC, 1991."

[steamedhams]

Do you know if the benchmarks are in VHDL??

I can only see BLIF which isnt ideal for what I want to do.