FPGA Benchmarking

[steamedhams]

I want to create a bunch on bench-marking RTL designs for testing different FPGA technologies.
This includes DSP, LUTs, DFF, memory..etc.

Currently, I see many tests using adders, multipliers, standard algorithms to compare different FPGAs.
I'd like to have a test that includes PLL, memory speed, routing delay time (oscillator ring with frequency counter inside the design).
I see this type of work done in academia but nothing is readily available.

I had the thought to cobble together some IPs from FuseSoC as a basis for such benchmark circuits.

 
Any thoughts?
Does anyone know if these already exist?

[pbernardi]

Benchmarking does not make sense for FPGA. You can just check the timings for target device at datasheet and compare.

Benchmarking is more a CPU thing, where you have many different architectures which cannot be compared directly - in most cases, CPU are seen as black-boxes.  But for FPGA, you can just compare the max. speed for a given block, as DSP/BRAM/LUT, for example.

A FPGA benchmarking can be created, of course. If well done, it should just give the expected result from device datasheet.

[Gribo]

It makes sense if other parameters are included.
For example,
For a specific FIFO (Insert your favorite standard) implementation, what is the % of resources utilized in a 10$ part from a specific series, at which fMax etc.

[asmi]

For a specific FIFO (Insert your favorite standard) implementation, what is the % of resources utilized in a 10$ part from a specific series, at which fMax etc.

Most modern FPGAs have hardware FIFOs, so no coding required. But even if they didn't, it would be testing mostly synthesis, place&route as opposed to actual device. Infact you won't even need to have a device in hand, because if P&R says a design can reach certain frequency, it will reach it for sure. Testing resources utilized is also difficult because not all devices have the same base block designs - for example, Lattice and Antel's Cyclone 4-5 parts have LUT4 blocks, while Xilinx 7 series have LUT6 (which can be configured to work as two LUT5's), the latter allows packing more logic into the same amount of base blocks.