Author Topic: FPGA BRAM power consumption, how to figure this out?  (Read 1130 times)

0 Members and 1 Guest are viewing this topic.

Offline steamedhamsTopic starter

  • Regular Contributor
  • *
  • Posts: 65
  • Country: fr
FPGA BRAM power consumption, how to figure this out?
« on: June 25, 2021, 09:19:27 am »
I am looking at the Xilinx estimation tool to try and figure out how they have arrived at their estimation.

For instance:
This is the basic equation they use for the BRAM.
VCC * (Number of BRAMs)* (PortA_clock * ((read_rate * bit_mA) + (write_rate * bit_mA)) + PortB_clock * ((read_rate * bit_mA) + (write_rate * bit_mA)))

They have determined the reading and writing of one bit to be approx 1 mA.
Then they have used a read and write rate.

How do you think they've determined such values? (Image attached)

I would really like to know how people come up with these numbers...

My thoughts:
I could open up spice then try and recreate the same circuit which will likely be way off. (Caps, resistors, transistor W/L)
Or
Physically measure the reading of data for a given BRAM block, then just estimate some valid numbers that aren't too far off.

Or ideally, I can do both and see how far off they are. Then I can use the simulated values and add the different as a percentage.

I would like to apply their approach to other FPGAs or even improve upon these estimations.
 

Offline actuallyjaseg

  • Contributor
  • Posts: 21
  • Country: de
    • jaseg.de
Re: FPGA BRAM power consumption, how to figure this out?
« Reply #1 on: June 29, 2021, 08:23:30 am »
To me, the formula looks like a first-order approximation (I'd assume current consumption will be non-linear in clock speed, VCC and temperature). I would assume they chose this approximation by guessing and then validating that reality stays within a certain error band of the approximation.

I'd be surprised if they did not simply measure these values using some minimal benchmark design. Program the chip with a design that continuously addresses all the BRAMs on the chip and has a read/write toggle from outside, then let it run for a second and average the chip's current consumption. Repeat for a couple chips from the same series. To take into account the effect of the benchmark's logic driving the BRAM, someone at Xilinx could simply take the routed design and remove the BRAMs from it, leaving everything else in place.

I would guess that they simulated the components of the BRAM, but never the whole block at once.
 
The following users thanked this post: steamedhams


Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo
Smf