Electronics > FPGA

FPGA design: bus size vs die size

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josuah:
I recently discovered that the CPU core was often a rather small size of a microcontroller.

Is it also true for the bus size?

· 8-bit sized bus is smaller: "input [7:0]" and "outputs [7:0]".
· 32-bit sized bus means extra logic to select 16-bit and 8-bit out of 32-bit, like Wishbone's SEL_I.

But does it have a significant impact upon LUT number (FPGAs) or die size (ASICs)?

See also: https://www.eevblog.com/forum/microcontrollers/tiny-mcu-architectures-avr-pic-8051-stm8-msp430-custom-risc/

ataradov:
Byte selects on their own do not add a lot of logic. Better designed peripherals would ignore them anyway, so it only matters for memories.

But obviously wider bus would take more logic than narrower bus even without additional byte select  signals.

It is hard to judge die area used by the bus, since it by definition has to go everywhere, so it ends up being spread all over the place.

And in more complicated designs there is more than one bus with bridges between them. This simplifies the routing and lets you use different bus types trading speed vs simplicity.

SiliconWizard:
The question is unclear.
Is it just "bus size" or the actual size of registers/ALU/...? Two different things.

Obviously if the data or instruction bus size is a different width from the register/instruction size, this will usually require additional logic. Potentially making things significantly more complex. Sure multiplexing data is not very expensive, but what can be is all the underlying logic required to make use of that, such as more instructions required, and/or handling unaligned instruction or data fetching, thus a larger core.

josuah:

--- Quote from: ataradov on November 17, 2022, 09:00:35 pm ---Better designed peripherals would ignore them anyway, so it only matter for memories.

--- End quote ---

Fascinating. Peripherals would then be 8-bit bus, with multiplexing in the rare case of 16/32-bit fetches/writes from a 32-bit CPU core.
Getting each peripheral simper/smaller sounds a good yield given their number in a typical MCU.
That will help me with my next FPGA designs.


--- Quote from: SiliconWizard on November 17, 2022, 09:07:43 pm ---Is it just "bus size" or the actual size of registers/ALU/...? Two different things.

--- End quote ---

I had no idea it was possible or practical to have register size different than bus size, as I thought instructions would go fill registers by issuing read/writes requests through a bus of their same size, providing atmoic read/writes to SFR.

I am focused on the "bus size", such as the [31:0] vs [8:0] of a DAT_I/DAT_O (in Wishbone terms).


--- Quote from: SiliconWizard on November 17, 2022, 09:07:43 pm ---Obviously if the data or instruction bus size is a different width from the register/instruction size, this will usually require additional logic. Potentially making things significantly more complex. Sure multiplexing data is not very expensive, but what can be is all the underlying logic required to make use of that, such as more instructions required, and/or handling unaligned instruction or data fetching, thus a larger core.

--- End quote ---

So the multiplexing involved would at least prevent increasing the peripheral size, while still increasing the core size.

Thanks all for the answers, once again!

ataradov:

--- Quote from: josuah on November 17, 2022, 09:22:55 pm ---Fascinating. Peripherals would then be 8-bit bus, with multiplexing in the rare case of 16/32-bit fetches/writes from a 32-bit CPU core.

--- End quote ---
No, on a good 32-bit MCU peripherals will use 32-bit registers. And byte and half word access would be prohibited or results undefined. 


--- Quote from: josuah on November 17, 2022, 09:22:55 pm ---I had no idea it was possible or practical to have register size different than bus size, as I thought instructions would go fill registers by issuing read/writes requests through

--- End quote ---
This is extremely simplistic view. This was  true in the 80s designs. Look at Cortex-M7 core. It is a 32-bit core, but it uses 64-bit AXI bus because it uses a dual-issue pipeline and 32-bit bus would be a constant bottleneck.

And core registers are separate from the bus by a lot of other logic (prefetch units, IO buffers, caches and stuff like this). There is no direct connection between them at all.

And there are no peripherals on this bus, only memories. All the peripherals are located on the slower buses, often behind multiple bridges.

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