Author Topic: FPGA EEVBlog segments / Xilinx buyer's remorse  (Read 17782 times)

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Offline Fsck

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Re: FPGA EEVBlog segments / Xilinx buyer's remorse
« Reply #25 on: May 21, 2014, 12:48:31 pm »
Some people seem to be losing sight of when you should use an FPGA, i.e. when it's too time-sensitive to do on a processor. If you can do it on a processor, then do so - only do stuff in HDL when the processor can't do it fast enough, or when an MCU's I/O isn't a good fit for the interfacing requirement.

In most cases an external MCU+FPGA will give the best balance between cost, power, and development effort. There will be cases where it makes sense to put the MCU on the FPGA, e.g. if you need tight coupling or a small MCU in a big FPGA, but I suspect these will represent a small minority of applications.

this isn't a "some people" thing, it's a "quite often" thing. people go "oooh, we can put everything in one package, let's do it!"

and then you also have the people who use a softcore with just a couple of trivial pieces of digital logic in an fpga instead of using something like a psoc.
"This is a one line proof...if we start sufficiently far to the left."
 

Offline legacy

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Re: FPGA EEVBlog segments / Xilinx buyer's remorse
« Reply #26 on: May 21, 2014, 01:06:28 pm »
Have a look at  ZPUino http://www.alvie.com/zpuino/ - 32-bit micro with an Arduino interface.

It is known to be not really working
 

Offline legacy

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Re: FPGA EEVBlog segments / Xilinx buyer's remorse
« Reply #27 on: May 21, 2014, 01:32:36 pm »
about VHDL and learning VHDL
what do you think about this tool ?
(green mountains direct vhdl, editor and simulator)
 

Offline miguelvp

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Re: FPGA EEVBlog segments / Xilinx buyer's remorse
« Reply #28 on: May 21, 2014, 02:45:52 pm »
about VHDL and learning VHDL
what do you think about this tool ?
(green mountains direct vhdl, editor and simulator)

I took a look and for $49 seems like a good price but their vhdl tutorials pale compared to resources available out there
For example you could get a DE0-Nano or other lower cost FPGA dev kit and get Quartus II for free. or just use Quartus II for free without an FPGA and simulate all you want.

Plus Altera's training has a lot of material, this is just part of it:
http://www.altera.com/education/training/curriculum/fpga/trn-fpga.html

Was tempted to download the Green Mountain software to see if they have a trial period, but didn't do it.
 

Offline legacy

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Re: FPGA EEVBlog segments / Xilinx buyer's remorse
« Reply #29 on: May 21, 2014, 07:33:04 pm »
mmm they are offering you "VHDL studio" for eval, 15 days for free.

i Altera and Xilinx are missing a good editor, SIGASI seems to be a valid one, unfortunately the free-license is limited to 32Kbyte of VHDL code for the whole project which is too poor for me.

About Modelsim … well i'd like to tryout the Mentor's one, never done, but i am tempted :D
 

Offline mikeselectricstuff

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Re: FPGA EEVBlog segments / Xilinx buyer's remorse
« Reply #30 on: May 21, 2014, 08:19:28 pm »
about VHDL and learning VHDL
what do you think about this tool ?
(green mountains direct vhdl, editor and simulator)
Bear in mind you can write and simulate VHDL & Verilog with any of the FPGA manufacturers' toolchains without needing any hardware. 
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Offline miguelvp

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Re: FPGA EEVBlog segments / Xilinx buyer's remorse
« Reply #31 on: May 21, 2014, 08:36:37 pm »
mmm they are offering you "VHDL studio" for eval, 15 days for free.

i Altera and Xilinx are missing a good editor, SIGASI seems to be a valid one, unfortunately the free-license is limited to 32Kbyte of VHDL code for the whole project which is too poor for me.

About Modelsim … well i'd like to tryout the Mentor's one, never done, but i am tempted :D

Agreed on Quartus II editor not being better, I mean it's good enough but what gets me is that I can't do a simple find in project unless I open every single file.

I have not tried to override the text editor yet, but I guess I should try that one of these days. It's under Tools/Options/Preferred Text Editor, with Sigasi being on that list, but since I have Notepad++ I might see what I can do with that, just tried it and it work but haven't really use it just know it works.

I've even looked at the Notepad++ API and it's simple enough for Windows. But Np++ has already Verilog and VHDL support as a language and it's free. No SystemVerilog (.sv) support yet but adding new language support is possible and probably already on the net.

As for the simulation modelsim-altera is fine for my needs and it's free as well, but you can override all that on a per project bases and plug in the tools you prefer for synthesis and/or simulation.

But my point is that for $49 you can get this:

http://parts.arrow.com/item/detail/arrow-development-tools/bemicrocv

and actually use it instead of just simulate :)

Edit: Ha, I convinced myself to get one even if I already have a Cyclone V E dev kit but this has standard GPIO's for LVDS instead of the high speed mezzanine connector that cost an arm and a leg. Well it's just a grade 8 speed so 333MHz max, and my Nano is grade 6 (faster) but for $50 had to get it :)
« Last Edit: May 21, 2014, 09:28:45 pm by miguelvp »
 

Offline nctnico

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Re: FPGA EEVBlog segments / Xilinx buyer's remorse
« Reply #32 on: May 21, 2014, 11:25:51 pm »
mmm they are offering you "VHDL studio" for eval, 15 days for free.

i Altera and Xilinx are missing a good editor, SIGASI seems to be a valid one, unfortunately the free-license is limited to 32Kbyte of VHDL code for the whole project which is too poor for me.
I have used Sigasi + Eclipse for a big project and it works excellent. Much better than the utterly useless 'notepad' clone in ISE. So far I used the trial license but if I need to continu the project I'll shell out €70 for using Sigasi another month.

I'm using GHDL + GTKwave for simulation. I know the newer IDEs have simulation but GHDL and GTKwave where there sooner for me. And I don't simulate entire FPGA designs; only partial blocks of logic to keep simulation time down.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline legacy

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Re: FPGA EEVBlog segments / Xilinx buyer's remorse
« Reply #33 on: May 21, 2014, 11:38:40 pm »
GHDL + GTKwave for simulation

that's fun for me, too
thank you for the suggestion
i am emerging them in my gentoo box
=)
 

Offline legacy

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Re: FPGA EEVBlog segments / Xilinx buyer's remorse
« Reply #34 on: May 21, 2014, 11:41:27 pm »
about gentoo & VHDL projecting using GHDL and GTKWave

you simply should have to emerge these two

Code: [Select]
sci-electronics/ghdl
      Homepage:      http://ghdl.free.fr
      Description:   Complete VHDL simulator using the GCC technology

Code: [Select]
sci-electronics/gtkwave
      Homepage:      http://gtkwave.sourceforge.net/
      Description:   A wave viewer for LXT, LXT2, VZT, GHW and standard Verilog VCD/EVCD files
 

Offline legacy

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Re: FPGA EEVBlog segments / Xilinx buyer's remorse
« Reply #35 on: May 22, 2014, 12:29:16 am »
See comments from sigasi blog

From my point of view, no problems at all
even if ..  GHDL is written in ADA and GNAT is not so friendly (especially on gentoo)
i am successfully emerging the whole
 

Offline nctnico

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Re: FPGA EEVBlog segments / Xilinx buyer's remorse
« Reply #36 on: May 22, 2014, 12:41:15 am »
See comments from sigasi blog
If you read the last remark on that page you'll see the article is outdated.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline miguelvp

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Re: FPGA EEVBlog segments / Xilinx buyer's remorse
« Reply #37 on: May 22, 2014, 12:52:08 am »
Downloading Sigasi Starter Edition because:

http://www.sigasi.com/sigasi-starter-edition

Sigasi Starter Edition
beats any existing VHDL editor
forever free
great editor for any size project
fully functional features from Sigasi Pro, for small projects

And I can configure Quartus II use that editor instead of the built in one, seems the 32K limit doesn't apply to the editor part of it.
 

Offline alex.forencich

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Re: FPGA EEVBlog segments / Xilinx buyer's remorse
« Reply #38 on: May 22, 2014, 04:37:29 am »
mmm they are offering you "VHDL studio" for eval, 15 days for free.

i Altera and Xilinx are missing a good editor, SIGASI seems to be a valid one, unfortunately the free-license is limited to 32Kbyte of VHDL code for the whole project which is too poor for me.
I have used Sigasi + Eclipse for a big project and it works excellent. Much better than the utterly useless 'notepad' clone in ISE. So far I used the trial license but if I need to continu the project I'll shell out €70 for using Sigasi another month.

I'm using GHDL + GTKwave for simulation. I know the newer IDEs have simulation but GHDL and GTKwave where there sooner for me. And I don't simulate entire FPGA designs; only partial blocks of logic to keep simulation time down.

I use Kate for editing, then iverilog + gtkwave for simulation.  I'm actually looking at MyHDL for Python based testbenches right now; should be a lot easier to write a good Python testbench and then do a cosimulation with iverilog as opposed to writing the testbench in pure verilog, especially for things like DMA over PCIe or Ethernet/IP/UDP/TCP.  Unfortunately, this won't work with the serializers and deserializers, only the interfacing logic.  I also have makefile toolchains for Xilinx ISE and Altera Quartus 2, along with Xilinx Coregen and Altera QSYS.  Good 'ole 'make' and 'make program' takes care of business.  Although for one design, it still takes about 4 hours to complete place+route (targeted to a Virtex 6 HXT 565). 
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Offline legacy

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Re: FPGA EEVBlog segments / Xilinx buyer's remorse
« Reply #39 on: May 22, 2014, 12:10:07 pm »
If you read the last remark on that page you'll see the article is outdated.

but VHDL is still written in ADA, and the most of things they have written are still valid.
btw interesting points, after all


yahoooooo i have emerged gnat-gcc on my co-nix (unix for windows, using gentoo-portage)
and i can use ghdl (which is written in ADA, so to compile ghdl you need gnat-gcc) :D

wonderful !!!

i also emerged GTKware, so i am fine on Windows, and linux too =)
 

Offline legacy

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Re: FPGA EEVBlog segments / Xilinx buyer's remorse
« Reply #40 on: May 22, 2014, 12:19:57 pm »
seems the 32K limit doesn't apply to the editor part of it.

are you sure about this ? i am toying with a vhdl project about a tiny SoC composed by these modules

Code: [Select]
+ top_level
  + cpu
  + ram
     + bram_s3e
  + rom_boot
     + bram_s3e
  + uart
     + rx
     + tx
     + baud_gen
  + timer 
  + port IO 
    + LCD
    + LED

very easy and tiny project, but Sigasi is telling me that i am out of 32Kbyte limit
it may be cause the cpu module is very long about lines of code  :-//
 

Offline miguelvp

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Re: FPGA EEVBlog segments / Xilinx buyer's remorse
« Reply #41 on: May 22, 2014, 02:37:13 pm »
If you enable talkback when it comes with the dialog to put a license then next time it will open it.

But it will bring a dialog about reaching the limit or something and to upgrade which you can dismiss and it  opens a webpage for getting a license. But if you tick the dont show this again it wont open that web page every time you open a project.

Works for me even on big projects. If you don't want to enable talkback then you are out of luck as far as I can tell.

Edit: but I don't think I have a single file that will generate 32K by itself. Will try to lump a bunch off modules into a single file later.

Edit2: so for large projects the standard edition goes into baseline mode. But it doesn't loose integration with Quartus II although it does with Xilinx, lucky me I use Quartus II.

http://www.sigasi.com/sigasi-pro-vs-starter-edition

I'm still trying to figure out what the talkback mode sends, maybe i'll do a packet capture.
« Last Edit: May 22, 2014, 03:38:48 pm by miguelvp »
 

Offline NYEngineer

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Re: FPGA EEVBlog segments / Xilinx buyer's remorse
« Reply #42 on: May 22, 2014, 02:51:10 pm »
Downloading Sigasi Starter Edition because:

beats any existing VHDL editor
forever free
great editor for any size project


Shame it doesn't support SystemVerilog and Verilog.
 

Offline Bassman59

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Re: FPGA EEVBlog segments / Xilinx buyer's remorse
« Reply #43 on: May 22, 2014, 06:26:09 pm »
i Altera and Xilinx are missing a good editor, SIGASI seems to be a valid one, unfortunately the free-license is limited to 32Kbyte of VHDL code for the whole project which is too poor for me.

A lot of us still use emacs and its excellent VHDL mode for source code editing.

 

Offline Bassman59

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Re: FPGA EEVBlog segments / Xilinx buyer's remorse
« Reply #44 on: May 22, 2014, 06:35:12 pm »
Enlighten me: how do you drive that LCD without a sequential-execution processor? It seems to me that converting integers to decimal, performing string processing, and iterating through each char and pushing it out to the LCD would be incredibly obtuse to write in Verilog/VHDL. Am I wrong/missing something? I agree in principle, I want to avoid using a soft core if there's a reasonable way of avoiding it.

I think there's a disconnect here.

If the right tool for the job is a microcontroller, then use a microcontroller and not an FPGA. If you want to drive an LCD or communicate over Ethernet or a UART or you want to run a PID loop or drive a motor, use a microcontroller.  Can you do all of those things in an FPGA? Yes. LCDs and UARTs are trivial, and doing an Ethernet stack in VHDL would be punishing.

If you need to interface to a high-speed image sensor or ADC then you will need to use an FPGA.

That you can implement a processor in an FPGA is interesting, but as I noted, those of us who've actually done it usually go back to a system with a standalone processor connected to the FPGA.

 

Offline alex.forencich

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Re: FPGA EEVBlog segments / Xilinx buyer's remorse
« Reply #45 on: May 22, 2014, 06:54:33 pm »
Actually, an Ethernet stack on an FPGA is not that bad of an idea. I implemented a UDP/IP stack in verilog in about a week that can run at 1G line rate, and it is very useful for getting data into and out of an FPGA. The only annoying part was the dang UDP checksum in the header, necessitating some FIFOs.
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Offline miguelvp

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Re: FPGA EEVBlog segments / Xilinx buyer's remorse
« Reply #46 on: May 22, 2014, 07:26:06 pm »
Actually, an Ethernet stack on an FPGA is not that bad of an idea. I implemented a UDP/IP stack in verilog in about a week that can run at 1G line rate, and it is very useful for getting data into and out of an FPGA. The only annoying part was the dang UDP checksum in the header, necessitating some FIFOs.

Check Microsoft Network Monitor and check their UPD parser implementation in npl  (Network Monitor Parser Language) it's kind of strange get your head wrapped around that language as is kind of like in between C and HDL of some sort. But it would be easy to translate their udp.npl to VHDL.

They use it to display the details on the packet capture and it's 529 lines of code. And that's just one protocol out of 385 they have :)

Hardware layer Teredo anyone?

Edit: Or better yet, hardware http server for your connected device :)
« Last Edit: May 22, 2014, 07:28:23 pm by miguelvp »
 

Offline nctnico

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Re: FPGA EEVBlog segments / Xilinx buyer's remorse
« Reply #47 on: May 22, 2014, 11:08:46 pm »
That you can implement a processor in an FPGA is interesting, but as I noted, those of us who've actually done it usually go back to a system with a standalone processor connected to the FPGA.
I'm not quite sure you can speak for everyone and technology is advancing rapidly. The more you put into an FPGA the bigger the demand for a CPU which does simple housekeeping tasks. You can also save a lot of gates because software re-uses logic much more efficiently. Another problem is transferring data between a host processor and an FPGA fast. A parallel memory bus will eat lots of pins and PCB area. PCI express, ethernet (direct MAC connection) or USB have their own set of problems. In the past the amount of memory blocks in an (entry level) FPGA was limited so you'd have to think twice about using a memory block to store software but modern ones have plenty of memory inside. IMHO the biggest hurdle is to setup a development eco system which allows easy debugging and uploading new software. In the project I mentioned earlier I use Xmodem to upload a binary image of the software into the processor's memory.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline miguelvp

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Re: FPGA EEVBlog segments / Xilinx buyer's remorse
« Reply #48 on: May 23, 2014, 01:12:15 am »
seems the 32K limit doesn't apply to the editor part of it.

are you sure about this ? i am toying with a vhdl project about a tiny SoC composed by these modules

Code: [Select]
+ top_level
  + cpu
  + ram
     + bram_s3e
  + rom_boot
     + bram_s3e
  + uart
     + rx
     + tx
     + baud_gen
  + timer 
  + port IO 
    + LCD
    + LED

very easy and tiny project, but Sigasi is telling me that i am out of 32Kbyte limit
it may be cause the cpu module is very long about lines of code  :-//

So after allowing the talkback under Window->Preferences->Sigasi->Talkback

It allows you to open projects beyond the 32K. More info about what Talkback is:
http://www.sigasi.com/sigasi-talkback

Where you enable talkback it has a link into what is sent to the server too, nothing to scary it seems.

Once you are past the 32K it goes into baseline mode like I mentioned on a previous post. More info about baseline vs free under 32K or Pro, here:

http://www.sigasi.com/sigasi-pro-vs-starter-edition

But as you can see in this popup when I hover over the 100% in red it shows this:



And one of the files in the project contributes to 55K by itself.

But I can use all the baseline features.

Edit: if I disable talkback then I get this every time I try to open a window.
« Last Edit: May 23, 2014, 01:20:58 am by miguelvp »
 

Offline rs20

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Re: FPGA EEVBlog segments / Xilinx buyer's remorse
« Reply #49 on: May 23, 2014, 01:32:05 am »
Enlighten me: how do you drive that LCD without a sequential-execution processor? It seems to me that converting integers to decimal, performing string processing, and iterating through each char and pushing it out to the LCD would be incredibly obtuse to write in Verilog/VHDL. Am I wrong/missing something? I agree in principle, I want to avoid using a soft core if there's a reasonable way of avoiding it.

I think there's a disconnect here.

If the right tool for the job is a microcontroller, then use a microcontroller and not an FPGA. If you want to drive an LCD or communicate over Ethernet or a UART or you want to run a PID loop or drive a motor, use a microcontroller.  Can you do all of those things in an FPGA? Yes. LCDs and UARTs are trivial, and doing an Ethernet stack in VHDL would be punishing.

If you need to interface to a high-speed image sensor or ADC then you will need to use an FPGA.

That you can implement a processor in an FPGA is interesting, but as I noted, those of us who've actually done it usually go back to a system with a standalone processor connected to the FPGA.

There is indeed a disconnect, but the disconnect is from my original question as OP. I have a devkit (Spartan-3E starter) without a hard CPU anywhere onboard (AFAIK, a correction on this point would be useful), so a microcontroller just isn't an available choice. Chucking a soft-core on there may well halve my available gates, and be ridiculous as an end-use solution. But for a dev-kit, it's different. At least I'm not punishing myself by trying to write string manipulation in Verilog, and I can focus on real FPGA-appropriate stuff once I have a basic soft core going.
 


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