Electronics > FPGA
FPGA EEVBlog segments / Xilinx buyer's remorse
Scrts:
--- Quote from: alex.forencich on May 22, 2014, 06:54:33 pm ---Actually, an Ethernet stack on an FPGA is not that bad of an idea. I implemented a UDP/IP stack in verilog in about a week that can run at 1G line rate, and it is very useful for getting data into and out of an FPGA. The only annoying part was the dang UDP checksum in the header, necessitating some FIFOs.
--- End quote ---
You can write 0x0000 there (or 0xFFFF - I don't remember) and this will pass as a valid checksum. It's specified in RFC standards and some of the devices doesn't generate the checksum at all.
legacy:
@miguelvp
understood, thank you :-+
alex.forencich:
--- Quote from: Scrts on May 23, 2014, 08:01:42 am ---
--- Quote from: alex.forencich on May 22, 2014, 06:54:33 pm ---Actually, an Ethernet stack on an FPGA is not that bad of an idea. I implemented a UDP/IP stack in verilog in about a week that can run at 1G line rate, and it is very useful for getting data into and out of an FPGA. The only annoying part was the dang UDP checksum in the header, necessitating some FIFOs.
--- End quote ---
You can write 0x0000 there (or 0xFFFF - I don't remember) and this will pass as a valid checksum. It's specified in RFC standards and some of the devices doesn't generate the checksum at all.
--- End quote ---
All zeros is also an option, yes. I had to calculate the length anyway, which is also in the header, so I figured I might as well implement the checksum as well. The module I have will accept a framed data input of indeterminate length on an AXI stream bus (series of bytes with a tlast signal indicating the end of the frame), add a UDP header with the specified ports, fill in the length and checksum as computed from the data, and then send the result to the next module on another AXI stream interface. The only trick is that the data neds to be stored in a FIFO while the length and checksum are calculated, then the header can be attached via a second parallel header FIFO and the packet sent on its merry way.
Scrts:
--- Quote from: alex.forencich on May 23, 2014, 08:25:37 am ---
--- Quote from: Scrts on May 23, 2014, 08:01:42 am ---
--- Quote from: alex.forencich on May 22, 2014, 06:54:33 pm ---Actually, an Ethernet stack on an FPGA is not that bad of an idea. I implemented a UDP/IP stack in verilog in about a week that can run at 1G line rate, and it is very useful for getting data into and out of an FPGA. The only annoying part was the dang UDP checksum in the header, necessitating some FIFOs.
--- End quote ---
You can write 0x0000 there (or 0xFFFF - I don't remember) and this will pass as a valid checksum. It's specified in RFC standards and some of the devices doesn't generate the checksum at all.
--- End quote ---
All zeros is also an option, yes. I had to calculate the length anyway, which is also in the header, so I figured I might as well implement the checksum as well. The module I have will accept a framed data input of indeterminate length on an AXI stream bus (series of bytes with a tlast signal indicating the end of the frame), add a UDP header with the specified ports, fill in the length and checksum as computed from the data, and then send the result to the next module on another AXI stream interface. The only trick is that the data neds to be stored in a FIFO while the length and checksum are calculated, then the header can be attached via a second parallel header FIFO and the packet sent on its merry way.
--- End quote ---
I did that on UDP reception using Altera :)
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