Xilinx Ethernet Network Client 101

[petersanch]

Hello All,
I want to make a network client using Xilinx Artix 7 or Spartan 6 series FPGA. The goal is to transmit a buffer from FPGA memory to the server periodically. The PC will host a UDP server at a fixed IP address and port and listen for the data.

There are multiple ethernet IPs in Vivado and ISE. Are any of them good for this purpose?
Can this task be done without a soft core processor on the FPGA?
Are there any simple examples to get started with something like this?


Cheers!

[asmi]

I don't know what's included in ISE, but in Vivado there are basically two Ethernet IPs - the one for 10/100 Mbps, another is TriMAC for 10/100/1000 Mbps. There are also IPs for 10G and above, but I haven't personally used them, so I can't say much except for the fact that they are also paid IP. Only first of those is free to use, another requires a license for production use (trial versions stop working after some time). A choice of IP to use depends on the hardware on your board, so you can't mix & match them as you like, because each standard uses different protocol to talk to the PHY chip. So essentially you pre-select which IP you will have to use when you purchase or design a board.

It's also possible to not use any of those cores at all, and design your own core instead. It's not a very complex task, because MAC doesn't actually do all that much in the OSI model, though it does require studying 802.3 standard to understand the role of MAC in the IP stack. It's supposed to assemble packets, calculate a checksum and send it off to PHY chip via one of PHY protocols (MII/RMII/GMII/RGMII/SGMII/QSGMII), also receive packets, check the checksum, optionally see if it's addressed to your host, and then pass it along to a higher layer. Typically this core is either going to use it's own internal buffers for sending and receiving packets (like EthernetLite), or stream packets via some kind of streaming protocol, with these stream typically utilizing DMA IP to actually read from/write to the memory (this is how TriMAC IP works).

As for whether it's possible to implement it without a softcore - of course it is, but I think that utilizing a Microblaze softcore is the easiest and fastest way to get the project off the ground.

[Morgan127]

The fastest and easiest to do this is to use a core from https://www.fpga-cores.com/.
Both Spartan and Artix are supported.
No processor is needed and it is a simple AXI stream interface. As a bonus you get programming and logic analyzer over ethernet also.
I recommend you to use Artix and Vivado and not Spartan 6 and ISE.

You can have a look at this example https://www.fpga-cores.com/tutorials/ethernet-on-arty-a7-board/

You can download everything.

[petersanch]

As for whether it's possible to implement it without a softcore - of course it is, but I think that utilizing a Microblaze softcore is the easiest and fastest way to get the project off the ground.

Is the purpose of the soft core to take care of the TCP/IP stack?

The fastest and easiest to do this is to use a core from https://www.fpga-cores.com/.
Both Spartan and Artix are supported.
No processor is needed and it is a simple AXI stream interface. As a bonus you get programming and logic analyzer over ethernet also.
I recommend you to use Artix and Vivado and not Spartan 6 and ISE.

You can have a look at this example https://www.fpga-cores.com/tutorials/ethernet-on-arty-a7-board/

You can download everything.

Cheers. Does Vivado/Artix handle networking better than Spartan 6/ISE?

[Morgan127]

The fastest and easiest to do this is to use a core from https://www.fpga-cores.com/.
Both Spartan and Artix are supported.
No processor is needed and it is a simple AXI stream interface. As a bonus you get programming and logic analyzer over ethernet also.
I recommend you to use Artix and Vivado and not Spartan 6 and ISE.

You can have a look at this example https://www.fpga-cores.com/tutorials/ethernet-on-arty-a7-board/

You can download everything.

Cheers. Does Vivado/Artix handle networking better than Spartan 6/ISE?

No Spartan 6 handles networking without problem. I recommend Vivado and Artix (or Spartan7) because ISE is no longer supported by Xilinx and if you start with FPGA I think you should start with the latest tools.
You can not use Spartan-6 with Vivado.
And it looks like FPGA-Cores also going in this direction. Their latest https://www.fpga-cores.com/cores/fc1004_rgmii/']RGMII/Gigabit Ethernet core[/url] is not released for ISE/Spartan.
Cheers!

[petersanch]

No Spartan 6 handles networking without problem. I recommend Vivado and Artix (or Spartan7) because ISE is no longer supported by Xilinx and if you start with FPGA I think you should start with the latest tools.
You can not use Spartan-6 with Vivado.
And it looks like FPGA-Cores also going in this direction.

Thanks

Any recommendations on the external ethernet PHY chip? Does the FPGA-Cores core or the Xilinx TriMAC(TEMAC) core work with any PHY chip as long as a supported bandwidth is chosen in the core? My understanding is there are configuration registers inside the PHY chips that might be different from chip to chip.

[Morgan127]

No Spartan 6 handles networking without problem. I recommend Vivado and Artix (or Spartan7) because ISE is no longer supported by Xilinx and if you start with FPGA I think you should start with the latest tools.
You can not use Spartan-6 with Vivado.
And it looks like FPGA-Cores also going in this direction.

Thanks

Any recommendations on the external ethernet PHY chip? Does the FPGA-Cores core or the Xilinx TriMAC(TEMAC) core work with any PHY chip as long as a supported bandwidth is chosen in the core? My understanding is there are configuration registers inside the PHY chips that might be different from chip to chip.

If you don't need more than 100Mbps I recommend you to use a PHY with RMII interface. I think any will work.
Typically you don't need to set the internal registers.
I have used KSZ8081RNB in several project and it works great. Single supply and integrated termination resistors.
1Gbps/RGMII PHYs are more complicated. More supply rails and needs trim clock phases etc.