And what about protocols like UDP?? Do these FPGAs have large FIFOs to ensure they capture everything??
In my previous company we worked on hardware-based eth packet parser. We had the packet header digested in few clock cycles using a FSM with no CPU intervention needed.
Sure, it costs quite some flops, but it was blazing fast compared to CPU accessing RAM and processing in SW. And of course, some support for fancy protocols (like encapsulation, FCoE and so on) were not implemented and still handled by SW.