Electronics > FPGA

FPGA internal logic analyzer

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promach:
1. I am using ISE Chipscope ILA as shown in the picture below. May I know how I actually use CONTROL0 and TRIG0 signals to capture the FPGA signal that I want ? Note: I am trying to debug on this DDR memory controller project at https://github.com/promach/DDR

2. I have written my own ILA module at https://github.com/promach/internal_logic_analyzer . However, I am not sure how to code the verilog module that transmits the data to host cpu as well as the cpu software that actually processes the internally captured FPGA signals/data and display them accordingly ?

hamster_nz:
One thing to watch out for is when you attach an ILA close to the edges of your FPGA design it can make quite dramatic changes to design timing.

It pays to compare the implementation reports and timing summary to check that weird things are not going on.

This is especially important if a design is o ly lightly constrained (e.g only the clocks are specified).

promach:
Why is the bitstream generated successfully without error even without icon module ?

hamster_nz:
Short answer is because the design is still valid.

The ILA connects "read-only" to the signals being probed and (silently) to the FPGA's internal JTAG chain. With out it you just get your un-instrumented design.

promach:
Why am I having "no driver" error as shown below ?

In other words, how should I drive the CONTROL0 signal ?

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