FPGA: PID controller (VHDL newbie)

[nctnico]

Just wanted to note, that Picoblaze is a product for Xilinx and seems intended to be used only by Xilinx users. I am not sure if it is legal to be used on other vendors FPGAs. Altera (Intel) seems to have some sort of NIOS softCPU.

Good point. Picoblaze is highly optimized for Xilinx anyway (it is a true work of art) but for non-Xilinx use there is a functionally identical portable version called 'Pacoblaze'. NIOS is a full blown CPU core which is much more complicated (and overkill for a relatively simple statemachine).

In my projects I create a way to change the Picoblaze program externally (so I don't need to go through the FPGA compilation process) and debug it's firmware. For small FPGA projects which compile in seconds it doesn't matter much but when the compilation starts to take serious time then it can be a fast way to develop.

[filssavi]

It's certain it wouldn't be able to reach the same frequencies and would eat up more resources.
Since you pretty much have it all figured out, I can't see what it would bring to the table.

The statement is true, but it completely misses the point, I see very very few instances where a digital PID controller working at such extreme frequencies can be actually usefull in real life (other than as a d**k measuring context), so the frequency advantage while technically true is not applicable

As for the resources, modern FPGA’s are so large that using a tiny soft core or two is not that much of an issue

EDIT: on the resources side, calling the processing unit a soft core is also very generous, as for most type of non adaptive controllers including Not only PIDs  but much more advanced stuff you can really get by without even having loops and jumps, as you are executing mostly just a series of math operations chained together, this also simplified the control unit design greatly (that means you will have to write your own assembler/compiler though as I think adapting LLVM to such a strange architecture would be quite strange

[Bassman59]

Just wanted to note, that Picoblaze is a product for Xilinx and seems intended to be used only by Xilinx users. I am not sure if it is legal to be used on other vendors FPGAs. Altera (Intel) seems to have some sort of NIOS softCPU.

Good point. Picoblaze is highly optimized for Xilinx anyway (it is a true work of art)

It's "highly optimized for Xilinx" because by writing it as instantiations of Xilinx primitives makes it impossible to directly port to other manufacturers' devices. (Or even newer Xilinx devices. Last time I used a PicoBlaze I was doing Spartan 3AN designs, so ...). That was the intent. The line about how doing so is for best performance is bullshit.

[nctnico]

Just wanted to note, that Picoblaze is a product for Xilinx and seems intended to be used only by Xilinx users. I am not sure if it is legal to be used on other vendors FPGAs. Altera (Intel) seems to have some sort of NIOS softCPU.

Good point. Picoblaze is highly optimized for Xilinx anyway (it is a true work of art)

It's "highly optimized for Xilinx" because by writing it as instantiations of Xilinx primitives makes it impossible to directly port to other manufacturers' devices. (Or even newer Xilinx devices. Last time I used a PicoBlaze I was doing Spartan 3AN designs, so ...). That was the intent. The line about how doing so is for best performance is bullshit.

You are not getting my points: Picoblaze is a very neat example of hand crafting primitives into something functional. That is why I wrote 'highly optimised'. Secondly I'm not writing about performance as in throughput (I litteraly wrote you won't get the highest throughput) but using a simple softcore (programmable statemachine) like Picoblaze / Pacoblaze can greatly reduce development time. Especially when synthesizing / building a new FPGA binary takes an hour or more.

[hamster_nz]

It seems to make sense to me to do PID in HDL with an FPGA if you need very low fixed, predictable latency.

When you introduce software on a soft-core CPU the control loop latency can change based on inputs. Aside from jumps in the code path, CPU instructions like division can take a different number of cycles, and then there might be interrupts...

Implementing the PID in HDL and also using the CPU for command and control seems a good idea to me.