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Electronics => FPGA => Topic started by: lintweaker on May 31, 2020, 11:03:57 am

Title: FPGA SD controller issues - Cross Domain Clock issue?
Post by: lintweaker on May 31, 2020, 11:03:57 am
FPGA novice here. I've build a PCB to use the Waveshare CoreEP4CE10 FPGA board with my DIY Z80 based computer and (try to) build some nice 'hw' for it.
Basic stuff like a free running timer, UART all work great but I am having trouble getting the SD controller (SPI mode) to work properly.

I re-used this VHDL SD Controller:
https://github.com/douggilliland/MultiComp/blob/master/MultiComp_On_RETRO-EP4/Multicomp-MPM/Components/SDCARD%20()/sd_controller_High_Speed.vhd (https://github.com/douggilliland/MultiComp/blob/master/MultiComp_On_RETRO-EP4/Multicomp-MPM/Components/SDCARD%20()/sd_controller_High_Speed.vhd)

Issues I encounter:
- reading a sector from SD is not reliable, the data is only partially correct
- somehow it want's me to read more then 512 bytes
- Writing only succeeds for a few bytes

The Z80 side of things runs at a mere 3.58MHz while the FPGA runs at 50MHz. Could these issues be related to cross domain clock issues?

BTW The DIY Z80 board talks to the Waveshare board via bi-directional level converters (TI SN74LVC8T245DWR)
Title: Re: FPGA SD controller issues - Cross Domain Clock issue?
Post by: rstofer on May 31, 2020, 02:18:31 pm
I know nothing about the project but that is some pretty nice code for the SD controller.  Very clean!

I didn't find a schematic but I wonder if all of the required pull-up resistors are in place.  Floating signals might not be helpful.  Maybe this will help:

https://www.mouser.com/catalog/specsheets/an10911.pdf (https://www.mouser.com/catalog/specsheets/an10911.pdf)

Sheet 2 lower right corner in this schematic:

https://reference.digilentinc.com/_media/reference/programmable-logic/nexys-a7/nexys-a7-sch.pdf (https://reference.digilentinc.com/_media/reference/programmable-logic/nexys-a7/nexys-a7-sch.pdf)
Title: Re: FPGA SD controller issues - Cross Domain Clock issue?
Post by: lintweaker on May 31, 2020, 02:42:55 pm
Thanks for the comments on the code but that is not my code  :) Also thanks for the schematics.

I did try with and without pullups on the SPI lines. Did not really matter. It seems that in SPI mode the pullups are not needed?

I just found project emulating a whole Z80 based computer (MSX) which also used a SPI SD card controller. There they fed the SPI controller just the low Z80 clock instead of the FPGA clock.
Just tried it, giving the SPI / SD controller the Z80 clock makes it work! Not use if I now run the SD card out of spec with such a low clock...
Title: Re: FPGA SD controller issues - Cross Domain Clock issue?
Post by: SiliconWizard on May 31, 2020, 03:19:56 pm
This piece of code is a master controller as far as I've seen.

You may be running into a clock domain crossing issue, but we'd need to see the rest of your code to figure it out. By itself, this SD controller doesn't seem to have any clock domain crossing, so posting it alone doesn't really help.
Title: Re: FPGA SD controller issues - Cross Domain Clock issue?
Post by: lintweaker on May 31, 2020, 05:19:25 pm
This piece of code is a master controller as far as I've seen.

You may be running into a clock domain crossing issue, but we'd need to see the rest of your code to figure it out. By itself, this SD controller doesn't seem to have any clock domain crossing, so posting it alone doesn't really help.
I've put up the schematic of my converter board and the Quartus II project on my github page.
https://github.com/lintweaker/z8ty-coreep4ce6-board (https://github.com/lintweaker/z8ty-coreep4ce6-board)

Note: this is a WIP  :)
Title: Re: FPGA SD controller issues - Cross Domain Clock issue?
Post by: SiliconWizard on May 31, 2020, 05:28:46 pm
Yes it definitely looks like a clock domain crossing issue. You're using signals synchronized to the SD controller's clock from the (I assume) Z80 domain which is on another clock. So if you use the same clock, the problem disappears.

If you want to do this (in order to get faster SD access), you'll need to resynchronize signals between the two clock domains.
Title: Re: FPGA SD controller issues - Cross Domain Clock issue?
Post by: lintweaker on June 01, 2020, 05:31:42 am
Yes it definitely looks like a clock domain crossing issue. You're using signals synchronized to the SD controller's clock from the (I assume) Z80 domain which is on another clock. So if you use the same clock, the problem disappears.

If you want to do this (in order to get faster SD access), you'll need to resynchronize signals between the two clock domains.
Thanks for the heads up, now on how to fix this. I guess I am going to need this a lot going forward with FPGA's...
Title: Re: FPGA SD controller issues - Cross Domain Clock issue?
Post by: SiliconWizard on June 01, 2020, 03:17:02 pm
Learning how to properly cross clock domains is invaluable for digital design in general. Good thing IMO you run into this, because you definitely WILL need that knowledge on a regular basis, and this is one of the most overlooked issue (IME) for beginners (and some more experienced designers alike!)

Keep in mind those issues are there even more often than you may think. Implementing a simple UART requires properly dealing with clock domain crossing (since your UART RX will be asynchronous, so by nature on a different clock domain.) I've seen many "naive" UART implementations not properly dealing with that and spectacularly failing (of course more or less randomly - that's often the nature of metastability issues), giving endless headaches.

Good reading. You'll find a lot of stuff to read on the topic. If you need further help, you can always come back, but I think learning by yourself first will be more profitable.
Title: Re: FPGA SD controller issues - Cross Domain Clock issue?
Post by: lintweaker on June 01, 2020, 05:01:22 pm
Thanks, I will probably be back after a few failed attempts  ;D
I you happen to have some reading material on the subject you can recommend...I would not mind...
Title: Re: FPGA SD controller issues - Cross Domain Clock issue?
Post by: SiliconWizard on June 01, 2020, 06:55:38 pm
https://filebox.ece.vt.edu/~athanas/4514/ledadoc/html/pol_cdc.html (https://filebox.ece.vt.edu/~athanas/4514/ledadoc/html/pol_cdc.html)
https://www.edn.com/synchronizer-techniques-for-multi-clock-domain-socs-fpgas/ (https://www.edn.com/synchronizer-techniques-for-multi-clock-domain-socs-fpgas/)

Look up "clock domain crossing" in general.