True HDMI for Tang Nano 9K

[hve]

Hi All,

So my initial question:

I am wondering if some HDMI sink ports are more unequal than others....

So I am currently experimenting with a Gowin FPGA that streams video and audio over HDMI. Nothing fancy yet.... but some hdmi sinks work and others don't:

- Now on a regular Dell monitor Dell P2421 monitor no issues, perfect video over 1.5 meter of cable, no audio of course because the thing does not have speakers...
- On my older Samsung TV the HDMI ports are labeled "HDMI1" "HDMI/DVI". On the "HDMI/DVI" perfect video and audio however nothing when i plug into the "regular HDMI" connector.
- On my newer Samsung TV with HDMI ports 1 2 3 also no output, while it recognizes the hdmi is connected it will just tell check cables....

My device has only tdms channels connected, no DDC or CEC wires...

So what is the deal here?
  Is it electrical incompatibility
  Or because there's no EDID handshake over DDC?
  Or maybe because i doe not stream HDCP encrypted content?

UPDATE - 2023-1-1
Nope, turns out we need to populate R1, in order to provide +5v and activate the pullups for DDC and CEC. Thanks Andryblack: 

Check R1 on Tang Nano 9k board, after soldering this jumper (near HDMI connector) my Samsung TV recognize signal and show image.

Turns out that it was indeed electrical incompatibility:

Quote on page 3, paragraph 1 of PTN3366 data sheet:

2.1 High-speed TMDS level shifting
 Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and
HDMI v1.4b compliant open-drain current-steering differential output signals

Your gowin FPGA IOs cannot do that, and the series caps driving the outputs only makes things worse.

See the functional diagram on page 5, figure 2 of PTN3366 data sheet.

The gowin can only properly drive the series cap AC coupled DisplayPort digital video standard and some monitor inputs which may be wired to an HDMI connector may also be DisplayPort compatible for those input lines.  This may be the only reason some HDMI/DVI monitors can function with your circuit.

So in this post I created an initial schematic that is intended to be plugged in to the Tang Nano Boards and should deliver True - open drain - compatible HDMI output for use in general TV sets and so on.
See post below  https://www.eevblog.com/forum/fpga/fpga-to-hdmi-variants/msg4482196/#msg4482196 design files attached for thos willing to exploit the idea...

Updated:
V1.1 Schematics and the PCB file are included in the zip file.
Just upload in https://easyeda.com/

[BrianHG]

Use the 99cent LVTTL/LVDS->TMDS HDMI translator cable driver IC in the circuit posted here:
https://www.eevblog.com/forum/fpga/hdmi-dvi-encoder-with-audio-smart-quartus-pll-integration-in-systemverilog/

All other coding is up to you.  Note that some monitor inputs will only accept DVI mode and they will ignore a HDMI signal.  Make sure you can switch between the 2.

My LG flatron monitor is an example.  The HDMI input works with both DVI and HDMI TX standards, but, it also has a DVI input which will only understand DVI mode exclusively.

[laugensalm]

What's your resolution?

This could have many reasons, but you'll definitely get a compatibility gain when supporting EDID and proper video mode configuration, although classical video modes should work everywhere. I've come across a monitor (a no-name unit) that required an EDID readout sequence in order to start syncing.
HDCP is not an issue here. With high pixel clocks though, timing issues or IP core deficiencies can be exposed and some monitors may refuse to display, some would glitch, etc. These cases are hard to determine without a sink being able to debug lane skews and other HDMI issues, let aside really expensive GHz scopes able to spot signal issues.

[hve]

Hi Brian,

I am using this board: https://wiki.sipeed.com/hardware/en/tang/Tang-Nano-9K/Nano-9K.html.

HDMI driver schematic is below:

The CEC and DDC/I2C port are unused now, only pull-up to 5V 

I am suspecting that consumer electronic TV sets require the EDID / HDCP handshake via DDC or will fail to service the signal..

[mon2]

Found this:

https://github.com/tmatsuya/i2c_edid

[hve]

Hi Laugensalm,

I am aiming for 1280x720x60 which should be quite standard.

Connecting the laptop to the TV I can readout the supported modes:

Code: [Select]

// Modeline "Mode 4" 74.250 1280  1390       1420     1650   720   725        730      750 +hsync +vsync
//                   pclk   hdisp hsyncstart hsyncend htotal vdisp vsyncstart vsyncend vtotal
Using the Sameer hdmi code repo https://github.com/hdl-util/hdmi/:

Slightly changed the mode parameters in 'hdmi.sv':

Code: [Select]

        4:
        begin
            assign screen_width      = 1280;
            assign hsync_pulse_start = 110;
            assign hsync_pulse_size  = 30; // 40;
            assign frame_width       = 1650;

            assign screen_height     = 720;
            assign vsync_pulse_start = 5;
            assign vsync_pulse_size  = 5;
            assign frame_height      = 750;
            assign invert            = 0;
        end

Yes will need to perform EDID readout I think...

[BrianHG]

I am suspecting that consumer electronic TV sets require the EDID / HDCP handshake via DDC or will fail to service the signal..

That is only true if you HDCP encrypt your video.  I dont believe you are doing that as it requires an extensive license agreement.  I have not bothered with EDID yet and have not had any problems getting a picture to work fine.

Additionally, I'm sorry, but the board schematic you are showing does not have an authentic TMDS cable driver.  It is a 'Jerry rigged' together solution which cannot be guaranteed to drive a HDMI or DVI compliant  signal down any length of cable.

If you want a proper TMDS, transition-minimized differential signaling cable driving specification for HDMI & DVI, then the easiest solution when wiring to a FPGA's LVDS differential output pairs is to use this NXP IC:
https://www.nxp.com/docs/en/data-sheet/PTN3366.pdf

Unless your FPGA has a specific IO mode designed to drive a pulled-up 3.3v DC terminated end-point at the other end of the cable, use the NXP IC listed above which does support this HDMI/DVI weird standard driver for you.  Trying to pull off what you have shown in your supplied schematic, like the DC filter caps with the diode clamping will offer spotty support at best with many monitors.

[hve]

I am suspecting that consumer electronic TV sets require the EDID / HDCP handshake via DDC or will fail to service the signal..

That is only true if you HDCP encrypt your video.  I dont believe you are doing that as it requires an extensive license agreement.  I have not bothered with EDID yet and have not had any problems getting a picture to work fine.

Hmm I was hoping for an other answer, as some sort of an EDID handshake would be relatively easy to implement.
I will hook up the scope this weekend in order to see what signal is actually on the pins.

Thank you Brian!


 

[hve]

Found this:
https://github.com/tmatsuya/i2c_edid

It is for the display end. Still maybe see to start of with proper matching...

[BrianHG]

Quote on page 3, paragraph 1 of PTN3366 data sheet:

2.1 High-speed TMDS level shifting
 Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and
HDMI v1.4b compliant open-drain current-steering differential output signals

Your gowin FPGA IOs cannot do that, and the series caps driving the outputs only makes things worse.

See the functional diagram on page 5, figure 2 of PTN3366 data sheet.

The gowin can only properly drive the series cap AC coupled DisplayPort digital video standard and some monitor inputs which may be wired to an HDMI connector may also be DisplayPort compatible for those input lines.  This may be the only reason some HDMI/DVI monitors can function with your circuit.

[hve]

Quote on page 3, paragraph 1 of PTN3366 data sheet:

2.1 High-speed TMDS level shifting
 Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and
HDMI v1.4b compliant open-drain current-steering differential output signals

Your gowin FPGA IOs cannot do that, and the series caps driving the outputs only makes things worse.

See the functional diagram on page 5, figure 2 of PTN3366 data sheet.

The gowin can only properly drive the series cap AC coupled DisplayPort digital video standard and some monitor inputs which may be wired to an HDMI connector may also be DisplayPort compatible for those input lines.  This may be the only reason some HDMI/DVI monitors can function with your circuit.

Totally right, I should have done my homework.
Lesson here is just because device has HDMI connector does not mean HDMI compatible.. Thanks Brian case solved.

[NiHaoMike]

Get one of those cheap HDMI repeaters to regen the signal.

[hve]

Added a schematic of HDMI converter module for the Tang Board as suggested by Brian:

Comments are welcome...

Schematic:


3D view:


The JSON files for use with https://easyeda.com/ are included in the zip feel free to experiment...

Comments are welcome..

[BrianHG]

Added a schematic of HDMI converter module for the Tang Board as suggested by Brian:

Comments are welcome...

     You also need to pass the 5v to the HDMI out connector. Some PC monitors use this to sense if the PC is powered on, IE should they go into deep sleep.  Others use it to auto-scan their multiple video inputs.

The HPD tells the PC/video out side if it should turn on the TMDS transmitter, otherwise it may not pass FCC as an open plug may be transmitting a 1.5GHz plus sub-band signals into open air.

I'm not sure who designed that Tang Nano 9K PCB, but, replacing the 2x diode protection ICs with the one NXP buffer would have cost less in the long run, offer true HDMI cable driving with it's own built in anti-static diode protection and offer true DDC I2C level shifting.

[BrianHG]

Get one of those cheap HDMI repeaters to regen the signal.

I guess he decided to build one.

[tchicago]

Is there any more generic PTN3366 -> HDMI breakout board that can be used with other FPGAs boards? (Maybe supporting lower resolutions if there are signal integrity constraints with lower frequency connectors)

I saw there was one from nockieboy in this topic https://www.eevblog.com/forum/fpga/hdmi-dvi-encoder-with-audio-smart-quartus-pll-integration-in-systemverilog/  but it has no PCB file to get gerbers from. 

[BrianHG]

Is there any more generic PTN3366 -> HDMI breakout board that can be used with other FPGAs boards? (Maybe supporting lower resolutions if there are signal integrity constraints with lower frequency connectors)

I saw there was one from nockieboy in this topic https://www.eevblog.com/forum/fpga/hdmi-dvi-encoder-with-audio-smart-quartus-pll-integration-in-systemverilog/  but it has no PCB file to get gerbers from.

The PTN3366 works from 240p to 1080p.
Plenty of stock exists everywhere, EG:
https://www.mouser.com/ProductDetail/NXP-Semiconductors/PTN3366BSMP?qs=%252BRKXB2WKlSdBGKoajmQSNw%3D%3D
https://www.digikey.com/en/products/detail/nxp-usa-inc/PTN3366BSMP/5981060?s=N4IgTCBcDaIAoBUByBmFA2dIC6BfIA

It's easy to wire, left side in, right side out, straight wires...
And with Nockieboy's and my code, even with crummy board-board din connector and unbalanced wiring, we got a Cyclone IV with it's normal LVTTL outputs to go as far as 1440x960, or 1280x1024.  (This is way beyond Altera's advertised limits for their normal IO toggle rate.)

Note that the PTN3366 does have internal pull-up resistors on the input side.  It may have been possible to directly wire it to the FPGA outputs without the DC filter caps, but, we did not experiment this far as the first solution worked right off the bat.

[BrianHG]

I saw there was one from nockieboy in this topic https://www.eevblog.com/forum/fpga/hdmi-dvi-encoder-with-audio-smart-quartus-pll-integration-in-systemverilog/  but it has no PCB file to get gerbers from.

This was the point where we finished the PCB: https://www.eevblog.com/forum/fpga/fpga-vga-controller-for-8-bit-computer/msg3328920/#msg3328920

Just ask nockieboy for the gerbers, or source files.  I guess he just thought that no one else would bother with that PCB designed for that FPGA dev board.

6gb/s 4k support would require TI's TDP158.  Note you are paying for the 6ghz HDMI 2.0b capable driver.

[hve]

Get one of those cheap HDMI repeaters to regen the signal.

I guess he decided to build one.

I ordered one for 2.5 USD just in case ...  
Don't look forward replacing the displayport connector with a HDMI-Male connector.

[hve]

I saw there was one from nockieboy in this topic https://www.eevblog.com/forum/fpga/hdmi-dvi-encoder-with-audio-smart-quartus-pll-integration-in-systemverilog/  but it has no PCB file to get gerbers from.

This was the point where we finished the PCB: https://www.eevblog.com/forum/fpga/fpga-vga-controller-for-8-bit-computer/msg3328920/#msg3328920

Just ask nockieboy for the gerbers, or source files.  I guess he just thought that no one else would bother with that PCB designed for that FPGA dev board.

6gb/s 4k support would require TI's TDP158.  Note you are paying for the 6ghz HDMI 2.0b capable driver.

1280x720P is good enough for me the Nano 9K board stays well below 1.2 GHz... 


Updated the design files to v1.1 if you are curious see the first post for the sources.

[andryblack]

- On my newer Samsung TV with HDMI ports 1 2 3 also no output, while it recognizes the hdmi is connected it will just tell check cables....

Check R1 on Tang Nano 9k board, after soldering this jumper (near HDMI connector) my Samsung TV recognize signal and show image.

[hve]

Thanks allot. Super this works!

Bridged the R1 with a wire. See attachment.

[andryblack]

Anybody success with HDMI/dvi RX on tang nano 9?