FPGA toolchain for Linux

[baremetal]

Hello everyone,

I would like to get recommendation on how to set up toolchain with Makefile on Linux distro for FPGA. I couldn't find any steps on how to set this up without some IDE.

Thanks,

[tsman]

You couldn't find any guides because you're asking an extremely vague question. What FPGA manufacturer? What model? The short answer is install the manufacturer provided software suite such as Xilinx Vivado and pay lots of money if your part isn't in the freely available version.

[rstofer]

Did you Google for 'xilinx makefile example' or something similar?  There are lots of examples for the older toolchain 'ISE'.  You might change the search to 'xilinx vivado makefile example'.  The Makefile approach was fairly common with ISE back about 10 years ago.

There is a Linux centric toolchain, search for: 'linux fpga tools'

So, yes, it can be done.

The generic tools under Linux often can't synthesize.  They can simulate standard logic but not vendor specific primitives.

IceStorm is open source, maybe it can be driven with a Makefile.

[FlyingDutch]

Hello,
 if you use Xilinx FPGA it might be interesting for you to take a look into "Petalinux":

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842250/PetaLinux

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841618/PetaLinux+Getting+Started

Kind regards

[james_s]

Why not just save a lot of time and trouble and use the vendor supplied IDE? I'm not aware of any viable alternative. ISE and Quartus are both available for Linux.

[nctnico]

Why not just save a lot of time and trouble and use the vendor supplied IDE? I'm not aware of any viable alternative. ISE and Quartus are both available for Linux.

The tools can be used from Makefiles. There is also hdlmake which can be used to automate building FPGA projects. It is not quite finished yet but it helps to share large projects which share common modules. With bigger projects the IDEs starts to suck especially when you want to share code between various projects.

[dgtl]

The vendor ides execute external binaries, these calls can be ported to makefile. Or alternatively, they support tcl scripts - ie Vivado can be run in batch mode given an tcl script. You can run that from your makefile. For our big projects, we generate tcl scripts from our build scripts and then run the tool in batch mode (no project files are stored in repositories, only system to resolve dependencies and generate tcl script to let Vivado generate its project depending on the configuration needed). This gives enough flexibility while being a single-step-make to reduce human errors to minimum.
There are some limitations, ie the components generated using their ip generation tools - afaik their configuration can not easily be modified with non-gui tools (parameters etc), so we need to store multiple variants and choose from them.

[NorthGuy]

Vivado is TCL based, so you can write your own scripts which can do practically anything - more than you could do in GUI. If you wish, you can use it as a TCL console, or you can invoke it to run a single TCL script - same as makefile. Of course, there's some learning curve involved.

[legacy]

I don't see points. What do you want to achieve?

[legacy]

With bigger projects the IDEs starts to suck especially when you want to share code between various projects.

I have never had problems with that. And I share a lot of VHDL code. What's wrong exactly?
Here, when I create a project, I manually import VHDL files from my library under versioning (git) into a local folder. And that's all I need to do. If I modify a local file, git and Beyond Compare (on Linux you use "Meld") report what has changed.

For simulating large project I am using ModelSim, which is the best ever for this.

[legacy]

we generate tcl scripts from our build scripts and then run the tool in batch mode

what have these tcl scripts have to do, exactly?

[filssavi]

Why not just save a lot of time and trouble and use the vendor supplied IDE? I'm not aware of any viable alternative. ISE and Quartus are both available for Linux.

There are various reasons:

1) FPGA IDE’s lag noticeably behind everything else on the planet (even VS code is significantly ahead of every fpga ide) in term of everything, especially dependency management
2) the integrated editor in fpga tools are almost at notepad level of sucking, using an external editor takes away the I in IDE and thus the things don’t make sense
3) altera hasn’t even managed to integrate a modelsim  front end and waveform viewer in the crappy mess they call An IDE
4) using VCS with gui projects is a nightmare, as the bloody things spread the settings and everything else among so many directories it isn’t even funny

And I could go on for hours

Thank god vivado has sane tcl scripting support from command line and I can create and delete projects on the fly as needed and check in only the tcl script

[legacy]

Thank god vivado has sane tcl scripting support from command line and I can create and delete projects on the fly as needed and check in only the tcl script

Why do you need a TCL script to create a project? Exactly what do you need to do?

[james_s]

I have not encountered these problems, ISE, Vivado and Quartus all have perfectly adequate text editors, it is a concept that has existed for decades, what more could one do to improve a text editor? Who cares if it's behind? With the current trend of software being constantly tinkered with, being in a constant state of flux like some perpetually half finished project car, chasing the latest UI fads which currently seems to involve hiding/removing frequently used features and inserting acres of useless white space to look "clean" or "uncluttered", being "behind" is something I've come to see as a benefit. I have 10+ year old software that is infinitely more usable than a lot of current stuff I encounter.

[NorthGuy]

I have not encountered these problems, ISE, Vivado and Quartus all have perfectly adequate text editors

Certainly not Vivado. Say, when you paste something, it automatically "improves" indentation, and then you need to fix it. I wish they had a simpler editor.

[nctnico]

I have not encountered these problems, ISE, Vivado and Quartus all have perfectly adequate text editors, it is a concept that has existed for decades, what more could one do to improve a text editor?

OMG! Those text editors suck badly. Try Eclipse + veditor for starters or Sigasi if you want to get luxureous. Being able to search through your project, having realtime syntax checking, browsing through the project, etc. Seeing which signals and components are used in a file. The list goes on and on. If you have a reasonably big project then having a real code development tool instead of notepad saves you a ton of time because the development environment helps you to navigate through the project.

[nctnico]

With bigger projects the IDEs starts to suck especially when you want to share code between various projects.

I have never had problems with that. And I share a lot of VHDL code. What's wrong exactly?
Here, when I create a project, I manually import VHDL files from my library under versioning (git) into a local folder. And that's all I need to do. If I modify a local file, git and Beyond Compare (on Linux you use "Meld") report what has changed.

Now try to share the same project using different IDEs from different vendors. The hdlmake I mentioned earlier can create project files for ISE, Vivado and Quartus from the same project for a specific build target. Also needing to import files manually into the IDE sucks especially if there are about 100 to 200 files and some conflict with eachother.

[legacy]

Now try to share the same project using different IDEs from different vendors.

I do without any problem, and I do it for a living.

Also needing to import files manually into the IDE sucks especially if there are about 100 to 200 files and some conflict with eachother.

100 files? here my projects (and I am talking about the largest one) have a max of 50 files. Importing them is no problem, neither with git nor for libraries. Files are hierarchically handled.

Which conflicts are you talking about?


Besides, I still have to understand WTF Makefile should have to do.

[legacy]

Sigasi if you want to get luxureous.

is it luxury or ... just envy? 

[filssavi]

The script creates the project, imports all the required dependencies, create and adds the block design etc.

This workflow has many advantages:
-Moving between machines is trivial as it only takes just 2 commands (git clone source make.tcl)
-everything is versioned through git, even the project settings, and my repository is not a mess of auto generated files Peppered across a massive directory structure
-code reuse and sharing between different modules is much easier, especially if interfaces between modules are not completely set in stone

[nctnico]

Sigasi if you want to get luxureous.

is it luxury or ... just envy? 

If you want to pay for it (which I don't because I need software to have perpetual licenses) then Sigasi is a tool which helps a lot during Verilog and VHDL development. I tried the Sigasi Eclipse plugin for a while and it works great. Veditor is a good alternative but not as extensive.

[james_s]

Certainly not Vivado. Say, when you paste something, it automatically "improves" indentation, and then you need to fix it. I wish they had a simpler editor.

I've only played with Vivado briefly, decided it was dog slow and that I'd rather spend my time making something than learning a different tool. I spend most of my time in Quartus and at least with that you can turn off the auto-formatting features. You can also edit the files in whatever editor you like and the IDE will offer to reload the modified file.

[rstofer]

Besides, I still have to understand WTF Makefile should have to do.

Among other things, it could call up the C compiler to create a .hex file to be included in the image to initialize the contents of BRAM.  This occurs somewhere during synthesis.

There is another way to patch the image with new memory contents using Data2Mem and this is a LOT faster than rebuilding the project.  But, still, a Makefile could drive the C compiler and Data2Mem.

[Macbeth]

I heard Altium is the one-stop-shop you are asking for regarding FPGA? Indeed, PCB layout should be a mere add-on afterthought optional extra.

Oh wait - I think that was when Dave worked there... 

[nctnico]

Also needing to import files manually into the IDE sucks especially if there are about 100 to 200 files and some conflict with eachother.

100 files? here my projects (and I am talking about the largest one) have a max of 50 files. Importing them is no problem, neither with git nor for libraries. Files are hierarchically handled.

Which conflicts are you talking about?

Actually the project I'm working on every now and then has over 500 VHDL files and some provide the same functionality for a different platform / build target.