Electronics > FPGA

FPGA VGA Controller for 8-bit computer

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BrianHG:

--- Quote from: nockieboy on October 14, 2021, 11:06:58 am ---I meant once the MAGGIE is redone, would it be possible to set the 'tile and palette dual port memories' clock speed via a parameter to match the target FPGA it's going to be working on?

As for the rest of your reply -  :o :o :o.  Seems some major changes to be done and I'm going to have to go away and read all that at least ten times over to try to understand it all.  ;)

--- End quote ---
Ok, maybe the better question I should ask is:
Are 2 tile layers + X graphic layers good enough for you?  (X being a parameter based on FPGA resources.)
Or, do you need more than 2 tile layers?
Note that a -8 Altera FPGA can only run it's blockram at 250MHz, so, that's less than the 297MHz requires for a 4:1 mux read running 720p.  Though, we might be able to do some fancy crap to work around this to get 3:1, but, how advanced do you want to go and the cheapest Lattice -6 can only run the core ram at 200MHz. (Not listed, just a guesstimate as only their highest speed 272MHz is in their data sheet.)

nockieboy:

--- Quote from: BrianHG on October 14, 2021, 11:22:32 am ---Ok, maybe the better question I should ask is:
Are 2 tile layers + X graphic layers good enough for you?  (X being a parameter based on FPGA resources.)
Or, do you need more than 2 tile layers?
Note that a -8 Altera FPGA can only run it's blockram at 250MHz, so, that's less than the 297MHz requires for a 4:1 mux read running 720p.  Though, we might be able to do some fancy crap to work around this to get 3:1, but, how advanced do you want to go and the cheapest Lattice -6 can only run the core ram at 200MHz. (Not listed, just a guesstimate as only their highest speed 272MHz is in their data sheet.)
--- End quote ---

I think two tile layers should be just fine.  I'm probably misunderstanding the value of tile layers, but afaik there's nothing they can do that a graphics layer can't and the tile layer was borne out of the need to fit an 80x25 character display into the small amount of block RAM we had available before DDR3?

BrianHG:

--- Quote from: nockieboy on October 14, 2021, 11:34:14 am ---
--- Quote from: BrianHG on October 14, 2021, 11:22:32 am ---Ok, maybe the better question I should ask is:
Are 2 tile layers + X graphic layers good enough for you?  (X being a parameter based on FPGA resources.)
Or, do you need more than 2 tile layers?
Note that a -8 Altera FPGA can only run it's blockram at 250MHz, so, that's less than the 297MHz requires for a 4:1 mux read running 720p.  Though, we might be able to do some fancy crap to work around this to get 3:1, but, how advanced do you want to go and the cheapest Lattice -6 can only run the core ram at 200MHz. (Not listed, just a guesstimate as only their highest speed 272MHz is in their data sheet.)
--- End quote ---

I think two tile layers should be just fine.  I'm probably misunderstanding the value of tile layers, but afaik there's nothing they can do that a graphics layer can't and the tile layer was borne out of the need to fit an 80x25 character display into the small amount of block RAM we had available before DDR3?

--- End quote ---

The difference is with the tile layers, to get a 256 color foreground/background display, for each line, we need to feed 320 bytes per line (80x4bytes) per line and the tile memory will do all the looking up in that 128kb blockram.  For graphics, that would be 640 bytes per line for 8 bit color.

But, with a blitter software font, not only do you need to display the 640 bytes each line, but graphically there is a new 640 bytes every line instead of a new 640 bytes every 16 lines.  And to do a blitter driven tile set into a normal graphics layer, you need to read from 1 section of memory, then write to another, 16 times for a 8x16 font.  And for every move and screen scroll, that's 32x the memory operations compared to the tile modes.  Regardless of blitter speed, if you are using the blitter to draw and fill in the tile section, that will run 32x faster to fill the screen.  And if you use the blitter to fill sections of the tile memory itself, you can animate 100s of characters/tiles simultaneously on display just by writing a few bytes without any other additional overhead.  With the tiles, you can draw huge tiled repetitive animated backdrops by blitting a few new tiles from upper DDR3 ram into the tile memory once every V sync without the Z80 even noticing anything happening.

If you wanted a 8 bit 256 color font, 8x16, 256 characters, that would be 32 kilobytes of ram.  You can create a 1024 character set with 128kb of ram, or, a 256 character set 32bit color font.  Mixes and matching fonts and color settings is also allowed.  Most likely, we will place 2 palettes at the output of the tile ram so each tile layer may have it's own color palette as well.

BrianHG:
With the geometry unit reading and writing to the DDR3, and the Z80 not generating errors, we can safely say that my DDR3 controller works with a Z80 and GPU.  We now just need to get the picture to come directly from the DDR3 with the new maggie.  Then think about optimizing the geometry unit to work as fast as possible when drawing on the DDR3 plus update it to render with 16bit coordinates and address 32bits so it may draw within the full 512mb of available ram.

nockieboy:

--- Quote from: BrianHG on October 14, 2021, 12:45:16 pm ---With the geometry unit reading and writing to the DDR3, and the Z80 not generating errors, we can safely say that my DDR3 controller works with a Z80 and GPU.  We now just need to get the picture to come directly from the DDR3 with the new maggie.  Then think about optimizing the geometry unit to work as fast as possible when drawing on the DDR3 plus update it to render with 16bit coordinates and address 32bits so it may draw within the full 512mb of available ram.
--- End quote ---

That'll make a huge difference as it means I won't be restricted by the block RAM size anymore - 640x480x8 here we come! Hopefully. ;)  Okay, cool - what do you want me to do?

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