Electronics > FPGA

FPGA VGA Controller for 8-bit computer

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BrianHG:
Micron might have one in their e.MMC line.  But right now, their website is messed up as I cannot see or select any part numbers including their DDR3 stuff.

BrianHG:
You can google: 'MMC card verilog simulation test model'

Read the comments in this resulting thread : https://www.edaboard.com/threads/sd-card-verilog-behavioral-model.35335/

nockieboy:

--- Quote from: BrianHG on November 28, 2021, 12:21:59 am ---You can google: 'MMC card verilog simulation test model'

Read the comments in this resulting thread : https://www.edaboard.com/threads/sd-card-verilog-behavioral-model.35335/

--- End quote ---

Yeah I found that thread last night; bearing in mind the comments are over 16 years old, I couldn't find anything of use on the Samsung website mentioned - that appears to be a dead end now.  Any information at denali.com is hidden behind a user login wall on the site -  I can't even do a search for relevant information before deciding whether I want to register an account, which I'm reluctant to do when the trail to this site is so cold. :horse:

Take a look at this more recent post https://www.edaboard.com/threads/sd-emmc-card-simulation-model.365970/ and it appears that denali is a dead-end too.

BrianHG:
Finally, it's here: BrianHG_DDR3 V1.5.
First, the new Z80 bus interface testbench...

Each new port on the DDR3 is a read and write port instead of the separate read ports, then separate write ports.

-PLUS- we now have a DDR3 shadow write TAP port:
// **************************************************************************************
// This Write Data TAP port passes a copy of all the writes going to the DDR3 memory.
// This will allow to 'shadow' selected write addresses to other peripherals
// which may be accessed by all the multiple write ports.
// This port is synchronous to the CMD_CLK.
// **************************************************************************************

This means, any peripherals writing to the DDR3 from any of the multi-ports are ordered and copied out to this port which can be tied to all the GPU control regs and palette rams.  So, blitting / accelerated mem copies from 1 ram location to a GPU control reg will have the same write access as the Z80 originally had.  Multiple prepared palettes, screen settings, or anything anywhere in ram or even on flash card can be GPU hardware written directly into the settings address without the Z80 having to do anything other than set the start & destination address with the number of bytes to be copied.

BrianHG:
Here we go, GPU with my BrianHG_DDR3 controller beta v15.
 (  :scared: All together 11084 lines of code just for the new DDR3...  :scared: )
No more timing violations with 5 ports @ 400MHz, and, there shouldn't be any even with all 16 ports in use (I hope)...

I also noticed that you made changes to the Z80_bus_interface on the last 'GPU_DECA_DDR3_new.zip' compared to my TB posted above.  I hope I got everything right in trying to catch and transfer all the changes, but you still need to verify these 2 settings:


--- Code: ---   .Z80_DELAY_WAIT_RI     ( 3       ), // 0 to 7, Number of CMD_CLK cycles to wait for DDR3 read_ready before asserting the WAIT during a Read Instruction Opcode cycle.
   .Z80_DELAY_WAIT_RM     ( 3       ), // 0 to 7, Number of CMD_CLK cycles to wait for DDR3 read_ready before asserting the WAIT during a Read Memory cycle.

--- End code ---

Check to see the lowest number which properly prevents the 'WAIT' from being asserted during a read cache hit condition.

Also check for the 'filled-box' graphical glitch which happens occasionally on the left most of a new line.

If everything works, you can try connecting your palette ram to the new 'Write Data TAP port'.  You will need to filter the address range for the palette and pass the appropriate write mask bits as the write data width is 128bits with 16 wmask bits.  You will also need to shift the write address.

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