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FPGA VGA Controller for 8-bit computer

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nockieboy:

--- Quote from: BrianHG on July 06, 2022, 11:52:36 am ---So, the authentic mode 0 480p doesn't work?
--- End quote ---

I actually haven't tested that mode yet.  Have a lot going on, so am having to prioritise.  I'll get to this soon, hopefully.


--- Quote from: BrianHG on July 06, 2022, 09:36:55 pm ---Also, what happened to the speckle dots?
--- End quote ---

I saw the blue lines again briefly yesterday, but that was for 2 seconds and haven't seen them since.  Like I said, they're very infrequent. :-//


--- Quote from: BrianHG on July 06, 2022, 11:52:36 am ---Did you get the line-out to run with the 1khz tone from copying the HDMI I2S output to the audio codec?
Note that since the line out is only stereo, you should only be using data bit 0, but the Mclk, Wclk, Sclk should match and there might be 1 high frequency control clock added to that.

You should be able to re-configure or make your own PLL clock replacement to match the HDMI audio PLL clock rate, but, add a few extra clock outputs for your sound generator module.

The HDMI audio serializer has a parallel data LUT table in it.  You will be taking that table, making sure you separate out the left and right, and make a new parallel 16bit stereo input port with said serializer to send raw parallel digital audio through the HDMI.
--- End quote ---

:-[ Okay, I've deviated from the plan very slightly in terms of the order of doing things.  I had a successful couple of hours yesterday, and got the synthesiser output wired into the HDMI audio feed and now get beeps out of the TV when I try to delete past the start of the screen (so basic audio is working in the DMI).  I figured that was an easy hit (and my end goal, ultimately), so I haven't yet started on linking the synth up to the DAC on the DECA board, as that looks to be a little more involved and will take me more time.

My focus today has been on trying to sort out the tuning/timing issues and getting music to play.  I'm able to play notes in the DMI, but can't get the CP/M program to play PT3s at the moment, which is a pain - so I'm debugging that.  Once that's done, I'll turn my attention to the DAC output.

The YM2149 module has some pretty specific requirements - some of which may still cause me issues.  Here's a snip of the text at the start of the module:


--- Code: ----- Clock, Clock-enable, and Sel.
--
-- The clk_i input should be the full-speed clock of the system, and
-- en_clk_psg_i must be a strobe (single clk_i tick) at the PSG operating
-- frequency.
--
-- This core can use a much faster clock-enable than the original PSG, however
-- the clock-enable frequency affects the output audio frequency directly.  If
-- producing sounds similar to the original ICs is desired, then using an
-- accurate input clock-enable is important.
--- End code ---

The clk_i input is fed by CMD_CLK.  The clock-enable is created by a module I wrote that takes the CLK_54 output from the VGA_PLL and divides it down to get a 1.78 MHz clock signal.  It then creates a strobe (with a pulse width of CLK_54) at 1.78 MHz frequency which is passed to the YM2149 module via en_clk_psg_i.

One issue is that the YM2149 module won't do anything until the rising edge of one of these strobes at 1.78 MHz.  This means it can miss entire I/O reads or writes from the host when a rising edge on en_clk_psg_i doesn't perfectly coincide with the right part of the host's I/O cycle.  To get around this, I've just OR'd the strobe with the control signal from the host to the synth, so a pulse is always generated at the start of an I/O op and is never missed.  This pulse is obviously out of frequency and the pulse width is wider than the normal strobe, but it seems to get the job done for the moment.

EDIT: I've added a zip with some key files in it used in the project to produce sound, including the updated project _top file linking the major parts together.

BrianHG:
If you wanted verilog, then look here: https://github.com/jotego/jt49
Includes test-benches.

BrianHG:

--- Quote from: nockieboy on July 07, 2022, 01:24:01 pm ---
--- Code: ----- Clock, Clock-enable, and Sel.
--
-- The clk_i input should be the full-speed clock of the system, and
-- en_clk_psg_i must be a strobe (single clk_i tick) at the PSG operating
-- frequency.
--
-- This core can use a much faster clock-enable than the original PSG, however
-- the clock-enable frequency affects the output audio frequency directly.  If
-- producing sounds similar to the original ICs is desired, then using an
-- accurate input clock-enable is important.
--- End code ---

The clk_i input is fed by CMD_CLK.  The clock-enable is created by a module I wrote that takes the CLK_54 output from the VGA_PLL and divides it down to get a 1.78 MHz clock signal.  It then creates a strobe (with a pulse width of CLK_54) at 1.78 MHz frequency which is passed to the YM2149 module via en_clk_psg_i.

One issue is that the YM2149 module won't do anything until the rising edge of one of these strobes at 1.78 MHz.  This means it can miss entire I/O reads or writes from the host when a rising edge on en_clk_psg_i doesn't perfectly coincide with the right part of the host's I/O cycle.  To get around this, I've just OR'd the strobe with the control signal from the host to the synth, so a pulse is always generated at the start of an I/O op and is never missed.  This pulse is obviously out of frequency and the pulse width is wider than the normal strobe, but it seems to get the job done for the moment.

EDIT: I've added a zip with some key files in it used in the project to produce sound, including the updated project _top file linking the major parts together.

--- End quote ---

I'll help you out here if you setup a modelsim workbench with these 2 modules with a 100mhz source clock.
No pll, just the divider plus a means of entering a few test sound commands.

Then we will worry about the precision reference 1.78 mhz needed for it internal tone generator from a 100MHz clock without a PLL as I have already created the fractional divider code in our HDMI serializer project.  In fact, that divider can be used multiple times to generate the second sample clock of 1.536/1.4112 MHz needed for the I2S sclk signal and it's shifter used for the 48/44.1khz sample rate of the HDMI audio and audio codec/dac.

Other methods exist to approach this, but everything on the 100MHz clock will operate the best.

An audio filter may be needed when going from the YM2149's 1.78Mhz sample rate to the 48KHz rate to prevent son weird tones, but this isn't a problem.

Our other choice is to run all the PSG at 54 MHz, with the same above code, to achieve decimal perfect clock dividers,

nockieboy:

--- Quote from: BrianHG on July 08, 2022, 09:13:42 pm ---I'll help you out here if you setup a modelsim workbench with these 2 modules with a 100mhz source clock.
No pll, just the divider plus a means of entering a few test sound commands.
--- End quote ---

Okay, no worries, it might take me some time to set up as I'm still extremely inexperienced with Modelsim, but I'll see what I can get done.


--- Quote from: BrianHG on July 08, 2022, 09:13:42 pm ---Then we will worry about the precision reference 1.78 mhz needed for it internal tone generator from a 100MHz clock without a PLL as I have already created the fractional divider code in our HDMI serializer project.  In fact, that divider can be used multiple times to generate the second sample clock of 1.536/1.4112 MHz needed for the I2S sclk signal and it's shifter used for the 48/44.1khz sample rate of the HDMI audio and audio codec/dac.

Other methods exist to approach this, but everything on the 100MHz clock will operate the best.

An audio filter may be needed when going from the YM2149's 1.78Mhz sample rate to the 48KHz rate to prevent son weird tones, but this isn't a problem.

Our other choice is to run all the PSG at 54 MHz, with the same above code, to achieve decimal perfect clock dividers,
--- End quote ---

I just threw together a divider based on a 28-bit counter, so I fully expect you'll have a better solution up your sleeve. ;)

BrianHG:

--- Quote from: nockieboy on July 08, 2022, 09:25:43 pm ---
--- Quote from: BrianHG on July 08, 2022, 09:13:42 pm ---I'll help you out here if you setup a modelsim workbench with these 2 modules with a 100mhz source clock.
No pll, just the divider plus a means of entering a few test sound commands.
--- End quote ---

Okay, no worries, it might take me some time to set up as I'm still extremely inexperienced with Modelsim, but I'll see what I can get done.


--- Quote from: BrianHG on July 08, 2022, 09:13:42 pm ---Then we will worry about the precision reference 1.78 mhz needed for it internal tone generator from a 100MHz clock without a PLL as I have already created the fractional divider code in our HDMI serializer project.  In fact, that divider can be used multiple times to generate the second sample clock of 1.536/1.4112 MHz needed for the I2S sclk signal and it's shifter used for the 48/44.1khz sample rate of the HDMI audio and audio codec/dac.

Other methods exist to approach this, but everything on the 100MHz clock will operate the best.

An audio filter may be needed when going from the YM2149's 1.78Mhz sample rate to the 48KHz rate to prevent son weird tones, but this isn't a problem.

Our other choice is to run all the PSG at 54 MHz, with the same above code, to achieve decimal perfect clock dividers,
--- End quote ---

I just threw together a divider based on a 28-bit counter, so I fully expect you'll have a better solution up your sleeve. ;)

--- End quote ---
I have linked here : https://www.eevblog.com/forum/fpga/vhdl-code-to-verilog-code/msg4129318/#msg4129318

Begin by downloading the .zip I posted and editing the setup/run.do to have the new file names and rename/edit the _tb file wire together and feed your sound modules.  You will notice that in the setup_xxx.do files, there is a different compile command for the .vhd VS the .sv files.

Get a waveform on the display and then we will work from there.

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