Electronics > FPGA

FPGA VGA Controller for 8-bit computer

<< < (726/729) > >>

nockieboy:
Eesh, didn't realise it had been this long - I've been flat out on work unfortunately.  I've had five minutes to look at this again and I think something is going on with Quartus optimising signals away.  I've added /* synthesis keep */ to the entirety of the IO_WR_STROBE and IO_WR_DATA buses and at least I can see those signals in SignalTap now and trigger on IO writes to the A and B input values to the FPU.  I can see that the values are getting written to the FPU, but the FPU's output (Q) is not changing.

I'm going to take a longer look at this signal optimisation when I have the time, but one thing I'm wondering is; does the FPU require a strobe on the enable line or is pulling it permanently high okay?

BrianHG:
Test a 32bit integer multiply.
I have a feeling the floating point unit isn't compiled properly leading to a dead module which simplifies out the source A&B input channels.

nockieboy:

--- Quote from: BrianHG on October 09, 2022, 11:25:36 am ---Test a 32bit integer multiply.
I have a feeling the floating point unit isn't compiled properly leading to a dead module which simplifies out the source A&B input channels.
--- End quote ---

Hmm.  Well, I set up an integer multiplier using the Quartus IP wizard and it seems to be working perfectly.  I can multiply two 32-bit numbers by writing their bytes to 4 IO addresses each, and can read the (cropped to) 32-bit output via a third set of four IO ports, as intended.

Must be something wrong with the FP_MULT instantiation...  :-//

BrianHG:
Heeehe....
Ok, I'll look for thee old original Altera FP functions before they combined them all into that single BS megafunction wizard which generates faulty non-functional functions.  It's like they have similar problems with their DDR3 controller.

You can post your question on Intel's website or:

Ok, here are the original direct call cores:
https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/mega/mega_list_mega_lpm_d1353e88.htm

Though, it was designed for Quartus 17 and earlier.

Now, Quartus is hiding these which have been replaced with the new garbage (ie: It don't function)  you can look at the old documents here:
https://www.manualsdir.com/manuals/746181/altera-floating-point.html?page=67
(I know the pipeline should be around 11 though 5 or 6 or 10 may work depending if low numbers like 5 or 6 can reach your operational 100MHz clock.)

nockieboy:
The new IP cores don't work? :o

I hadn't checked the results of the previous test, it was enough that the output had changed and actually had a value in it for me. :-DD

I'm compiling the project again as I write this (it's taking over 5 minutes per compile now), with IP files in the right folder.  Using these IP cores is a no-no then?

Navigation

[0] Message Index

[#] Next page

[*] Previous page

There was an error while thanking
Thanking...
Go to full version