FPGA VGA Controller for 8-bit computer

[BrianHG]

 Put in the extra effort and use at least the 'EP4CE15E22C8' fpga.  You get all 15 maggie layers, and enough free logic gates to add sprite collision detection or/maybe and semi-translucency between all layers.

[nockieboy]

Ok, here are the actual limits of each intel FPGA as I compiled your project with these chips:

Code: [Select]

-----------------------------------
EP4CE6E22C8
NUM_LAYERS = 7
ADDR_SIZE = 15
NUM_WORDS = 24576

Logic cells = 95% full
Remaining 1kbyte blocks = 5.
-----------------------------------
EP4CE10E22C8
NUM_LAYERS = 13
ADDR_SIZE = 16
NUM_WORDS = 40960

Logic cells = 96% full
Remaining 1kbyte blocks = 5.
-----------------------------------
EP4CE15E22C8
NUM_LAYERS = 15
ADDR_SIZE = 16
NUM_WORDS = 53248

Logic cells = 75% full
Remaining 1kbyte blocks = 3.
-----------------------------------
EP4CE40F23C8N OR EP3C40Q240C8N
NUM_LAYERS = 15
ADDR_SIZE = 17
NUM_WORDS = 122880

Logic cells = 30% full
Remaining 1kbyte blocks = 5.
-----------------------------------
Num_words is the bytes of available GPU display ram, + another 1024 for the palette.
Num_layers is the available display windows/sprites.  By now, you know what that means...

You know, the CE10 isn't looking that bad an upgrade at all.  Get's me another 6 layers, almost doubling the sprite count over the CE6.

I was wrong about the 'EP4CE15E22C8', you actually make it to 53.248kb instead of 48kb.
The cyclone III makes it to 122.88kb + space and IO pins for a 128mb or 1gb DDR2 Dram + another 3 MAGGIE layers for the Dram's contents (18 total MAGGIEs), but, your Z80 has so little address space that the 1gb may be too much.

Would be easy enough to page the 1gb into the 512KB 'window' available to the Z80, if I could find a use for all that RAM...

Since you are using the slowest -C8 versions, and, you need a C7, or even a -C6 for the higher densities, I recommend replacing the 1.2v regulator for an adjustable one and adjust it for 1.35v.  This will make a C8 perform somewhere inbetween a C7 and C6 which would be perfect.  Though, my GPU design, there are only a few critical address paths in the FPGA, so it still wont get warm or draw too much current over driving the VCCint to 1.35v.

Righto, so scrub the 1.2v regulator and replace with an adjustable set to 1.35v.  Also, add in a 3.3v 'analogue' sourced from the 5v for the ADV7125.  Am I right in thinking the 'analogue' 3.3v source is just a well-filtered, but otherwise identical, source to the existing 3.3v in the Microcom, but dedicated to the ADV7125 and sharing a ground with it?  The ground will still have to meet up with the primary ground on the system at some point?

[nockieboy]

Put in the extra effort and use at least the 'EP4CE15E22C8' fpga.  You get all 15 maggie layers, and enough free logic gates to add sprite collision detection or/maybe and semi-translucency between all layers.

Hmm.. okay, have ordered one - will perfect the board design for the CE10 when I get a chance and then re-do it from the CE15.

[BrianHG]

Put in the extra effort and use at least the 'EP4CE15E22C8' fpga.  You get all 15 maggie layers, and enough free logic gates to add sprite collision detection or/maybe and semi-translucency between all layers.

Hmm.. okay, have ordered one - will perfect the board design for the CE10 when I get a chance and then re-do it from the CE15.

Did you read Intel's data sheet and look at the pin planner for the CE15?  Make sure you have enough IOs.
Using the dedicated clock inputs the way I mentioned will give you 6 new free IOs, but, I think that with the CE15, you loose 6 IO since they change into power supply pins.

Also, re layout the DAC so it's analog out face the VGA connector directly, with proper GND return traces for the VGA connector's analog RGB GND return signals.  Also wire the 75ohm resistors properly within that return path.  Read my PCB design notes a few pages up.  The DAC draws so little current that you can use a simple RC filter for it's 3.3v regulator.

[nockieboy]

Did you read Intel's data sheet and look at the pin planner for the CE15?  Make sure you have enough IOs.
Using the dedicated clock inputs the way I mentioned will give you 6 new free IOs, but, I think that with the CE15, you loose 6 IO since they change into power supply pins.

Looks like you lose 10 IOs - I can't absorb that loss on the board, even using the clock inputs as you've suggested, without losing the SD card interface. I'll stick with the CE10 for the moment and see if I can get that working and make use of the SD interface with that.  You queried the interface method to the SD socket previously - is there a better way I can connect it up to utilise the remaining handful of IOs I have on the CE10?

Also, re layout the DAC so it's analog out face the VGA connector directly, with proper GND return traces for the VGA connector's analog RGB GND return signals.  Also wire the 75ohm resistors properly within that return path.  Read my PCB design notes a few pages up.  The DAC draws so little current that you can use a simple RC filter for it's 3.3v regulator.

Okay, will give that a try.  I have a couple of days off after tomorrow, hopefully can get the PCB re-organised then.  I guess if I'm moving the DAC to sit above the VGA socket, the resistors will be closer anyway, but I'm not 100% on what 'properly' entails.   Is it just maintaining a solid ground plane all around the resistors and VGA socket or do I need to consider anything else as well?

[BrianHG]

Did you read Intel's data sheet and look at the pin planner for the CE15?  Make sure you have enough IOs.
Using the dedicated clock inputs the way I mentioned will give you 6 new free IOs, but, I think that with the CE15, you loose 6 IO since they change into power supply pins.

Looks like you lose 10 IOs - I can't absorb that loss on the board, even using the clock inputs as you've suggested, without losing the SD card interface. I'll stick with the CE10 for the moment and see if I can get that working and make use of the SD interface with that.  You queried the interface method to the SD socket previously - is there a better way I can connect it up to utilise the remaining handful of IOs I have on the CE10?

Run the DAC at 18 bit.   You get 6 additional IOs + the other 6 on the dedicated clock inputs.
Your maximum palette has only 6 bits on the green anyways with 5 bit on the blue & red.

[BrianHG]

Here is a home made Lattice LFE5U-45 board, but, made with the 381 pin BGA.  The advantage using the 384 BGA is you can use the Lattice LFE5U-45 1.9megabit, or the LFE5U-85 3.7megabit interchangeably.  It's done in Kicad and the boards are home assembled.



Kicad project files: https://github.com/gregdavill/ButterStick

Example daughter board:

[SiliconWizard]

Here is a home made Lattice LFE5U-45 board, but, made with the 381 pin BGA.

Nice project!

[BrianHG]

Here is a home made Lattice LFE5U-45 board, but, made with the 381 pin BGA.

Nice project!

Just so we are clear, it is not my project.  But the presenter illustrates how easy it is to mount and bake a 0.8mm BGA using a stencil and solder paste.  And how if you watch him, the initial error in alignment, and centering of the BGA is not a problem.

[nockieboy]

Okay, here's the latest on the power supplies for the FPGA.  3.3VA is the supply for the DAC - you say it needs some sort of filter on the output - mentioned either RC or RLC.  I don't know enough about this stuff to decide which to use and what values I'd need.  Any suggestions welcome. 

[BrianHG]

RC filter the 5v input to the DAC's 3.3v regulator.
10 ohm, 0805, or 1206 for safety and 10uf should do.
Remember positioning and layout of the analog end...

Note that there are chokes and filters better suited for this, but your dac only draws 70ma max and a large enough resistor and cap are as cheap and dumb as it gets.

You can always use the same LC filters which you are using for the FPGA PLL analog supply.

[BrianHG]

Okay, here's the latest on the power supplies for the FPGA.  3.3VA is the supply for the DAC - you say it needs some sort of filter on the output - mentioned either RC or RLC.  I don't know enough about this stuff to decide which to use and what values I'd need.  Any suggestions welcome. 

The RC filter feeds the power into the regulator so that the regulator wont transmit high frequency ripple through it and the output will always be 3.3v, even with a voltage drop across the resistor.
You are using an analog regulator, so with no high frequency ripple entering the 3.3v regulator, the output should be clean as the regulator should be grounded next to the DAC itself.

[BrianHG]

RC filter the 5v input to the DAC's 3.3v regulator.
10 ohm, 0805, or 1206 for safety and 10uf should do.

To do things right, you can always replace the resistor with the correct 0805/1206 ferrite bead or inductor.

[nockieboy]

To do things right, you can always replace the resistor with the correct 0805/1206 ferrite bead or inductor.

Okay, so a 10 ohm ferrite bead can replace the resistor, or what value would I need for an inductor equivalent?

[nockieboy]

[BrianHG]

To do things right, you can always replace the resistor with the correct 0805/1206 ferrite bead or inductor.

Okay, so a 10 ohm ferrite bead can replace the resistor, or what value would I need for an inductor equivalent?

Until you can find the spectrum of the noise on your 5v supply, you cannot exactly tell.  The 10 ohm is a blanket low pass filter.  Though, voltage noise feeding the regulator input below a certain frequency begins to be rejected by the regulator electronics itself and you can tune or choose a ferrite to choke out all frequencies above that range.

What you have is ok.  When you build the PCB, all you need is to do is make an all white screen and make sure the regulator input is at least 4.2v approximately.  If not, just shrink the 10 ohm to 5 ohm.

The advantage of a ferrite is that it may have a DC resistance below 5 ohm, or even below 1 ohm, but as the frequency noise in your 5v supply increases, the series resistance increases dramatically according to the ferrite's datasheet chart blocking that signal from penetrating through.

Look up ferrite datasheets for these charts and look up your regulator's supply rejection ratio VS frequency to see where you want your ferrite to actually be at a really high resistance.

Change your 10uf to 100nf since it is non-polarized and add a 10uf in parallel.  You need both as the 10uf filters a lower frequency band white the 100nf/0.1uf cleans up the higher frequencies.

Also set the core VCCint to 1.3v.  1.35 is overkill and you want a touch of safety margin as each regulator and resistor precision may have a bit of error.

[nockieboy]

Okay, here's the power supplies for the FPGA:



On a slight tangent, taking 6 IOs (2 LSBs from each colour channel) will just about make up for the loss of 10 IOs on the CE15.  With the addition of the BLANK signal and the DAC CLK output, I don't have any free IOs on the CE10.  So if I move the key command signals (can't do all of them - non-critical signals like IORQ and RESET will have to go to normal IOs) to the FPGA's dedicated clock inputs, that will free up 5 IOs, plus the 6 from the colour output will give me 11 - so it'll be close, but I should be able to cater for the CE15.

Have attached latest schematic for info - still have yet to confirm that all the IO connections are valid and will work as intended.

[BrianHG]

I am just curious about the 2 pll analog GNDs going through those 2 ferrite beads.  I have never done that in my designs and I have not seen that elsewhere.  If your bottom layer is mostly a GND plane under the FPGA, you shouldn't need it.  However, can you show me a link to a third party design which uses it as personally I though something like this might actually create problems under some circumstances.  The ferrite on the +2.5v for the PLL is correct.

[BrianHG]

Have attached latest schematic for info - still have yet to confirm that all the IO connections are valid and will work as intended.

You only have 3 GND pins on your system expansion headers.  It is optimum to have 1 GND pin for every IO data pin for best results.  However, with your design's low frequency and low power, 4:1 or 5:1 should be fine.

[nockieboy]

I am just curious about the 2 pll analog GNDs going through those 2 ferrite beads.  I have never done that in my designs and I have not seen that elsewhere.  If your bottom layer is mostly a GND plane under the FPGA, you shouldn't need it.  However, can you show me a link to a third party design which uses it as personally I though something like this might actually create problems under some circumstances.  The ferrite on the +2.5v for the PLL is correct.

I've just copied the design from the EasyFPGA dev board schematics for the board I'm currently using - I figured it would be a good place to start from, considering the dev board seems to work fine. 

Dev board schematic attached below.  Of course, I don't know if this is a 1:1 of the actual, physical dev board I'm using - I found it on the net by searching for the dev board name, but the part numbers match up.  It looks as though the ferrite beads on the physical board are actually just links - they look like SMD resistors (black) with a '0' on them, so 0R links.  Looks like no ferrite beads were used. 

[nockieboy]

Latest 2-layer PCB design with changes made to position of the DAC, number of colour bits to the DAC, etc. (I've dropped the two LSBs from each channel).

Has taken me an hour or two to get component positioning/orientation in a way that allows a successful auto-route.  Still had to wire two of the power feeds to the FPGA manually.

I haven't bothered working on ground planes yet - I thought I'd seek some feedback on the positioning of the DAC and those pull-down resistors for R, G and B before I start stressing about ground plane placement.

[nockieboy]

For DAC_CLK (the pixel clock output from the FPGA) I've got two PLL output pins I can use, according to the pin manager in Quartus for the EP4CE10; one for PLL1 and one for PLL2.  The PLL2 output is preferable as it's closest to the DAC (it's currently used by R4 in the red channel to the DAC) - but, and this may be a stupid question - how do I know if PLL2 is used and, if not, how would I force Quartus to use it or will the router manage that by itself when it sees I've connected the clk output from the PLL to a PLL2 output?

[BrianHG]

For DAC_CLK (the pixel clock output from the FPGA) I've got two PLL output pins I can use, according to the pin manager in Quartus for the EP4CE10; one for PLL1 and one for PLL2.  The PLL2 output is preferable as it's closest to the DAC (it's currently used by R4 in the red channel to the DAC) - but, and this may be a stupid question - how do I know if PLL2 is used and, if not, how would I force Quartus to use it or will the router manage that by itself when it sees I've connected the clk output from the PLL to a PLL2 output?

If you System clock in is on PLL#1's dedicated clock input, ie 50MHz, use PLL#2.  This way, currently, if you have a nice multiple output clock, ie 25Mhz, 125MHz &250 Mhz current clocks, Quartus will automatically connect PLL#1 to #2 to generate the PLL output.  If you wan to use a SMPTE compatible 480p, IE 27Mhz pixel, 135Mhz core, 270Mhz core ram, You can make PLL #1 in Quartus convert 50MHz to 270MHz, then use PLL#1 to drive PLL#2 to generate the nice required multiples 27,135,270MHz.

So yes, connect the DAC's CLK input to PLL #2's output as it offers your best flexible path.

[BrianHG]

Latest 2-layer PCB design with changes made to position of the DAC, number of colour bits to the DAC, etc. (I've dropped the two LSBs from each channel).

Has taken me an hour or two to get component positioning/orientation in a way that allows a successful auto-route.  Still had to wire two of the power feeds to the FPGA manually.

I haven't bothered working on ground planes yet - I thought I'd seek some feedback on the positioning of the DAC and those pull-down resistors for R, G and B before I start stressing about ground plane placement.

Ohh boy, are you auto routing and auto placing this?

Move the VGA connector to the right a little.

Make the DAC at 90 degrees so that the analog out faces the VGA plug.
Make the DAC's 75 ohm resistors and dac wiring straight to the VGA plug.  Make the proper VGA plug's Analog R&G&B  GND return pin paths feed on the top through/wired to the other side of the 75 ohms and to the DAC's R&G&B negative signals.  Place as many of the decoupling caps on top to the sides of these signals.  Also, you should be using 0603 parts, or if your hands are steady enough,  go for 0402 for these DAC components so everything is in a straight line.

Under the dac, bottom layer, a fill GND should be used throughout.    Use 2 adjacent VIAs for every GND connection to the top layer.

For a 2 layer board, this should make a really good analog signal for your frequency range.

Remember, match red's return GND signal path with red's 75 ohm resistor, then to the dac's inverted red GNS input.  You do not want a signal reflection crosstalk across your video outputs since you didn't match GNDs.  The GND plane feeding the VGA connector's GND pins will be good enough for your bandwidth.

[nockieboy]

Ohh boy, are you auto routing and auto placing this?

Is there any other way when things start getting complicated?

I've manually placed all the components, but I am auto-routing otherwise it'd take me days to do the board manually?  Is there a better way, then?