FPGA VGA Controller for 8-bit computer

[BrianHG]

Ohh boy, are you auto routing and auto placing this?

Is there any other way when things start getting complicated?

I've manually placed all the components, but I am auto-routing otherwise it'd take me days to do the board manually?  Is there a better way, then? 

LOL, see my attached 100% manual routed 8 layer board...

I expect you to at least route the crucial analog traces and Power and GND thick traces and force multiple vias there.
You may route the rest automatically, however, your "puny" 2 layer PCB is a 30 minute manual job.

Look at the total stats on my all manual routed attached .pdf.

[nockieboy]

LOL, see my attached 100% manual routed 8 layer board...

I expect you to at least route the crucial analog traces and Power and GND thick traces and force multiple vias there.
You may route the rest automatically, however, your "puny" 2 layer PCB is a 30 minute manual job.

Look at the total stats on my all manual routed attached .pdf.
(Attachment Link)

You may route the rest automatically, however, your "puny" 2 layer PCB is a 30 minute manual job.

It may be a 30-minute job for a professional like yourself, but remember my experience with electronics is pretty minimal at best.  I've only got this far on the desire to learn and stubbornness bordering on stupidity. 

[nockieboy]

Move the VGA connector to the right a little.

Make the DAC at 90 degrees so that the analog out faces the VGA plug.
Make the DAC's 75 ohm resistors and dac wiring straight to the VGA plug.  Make the proper VGA plug's Analog R&G&B  GND return pin paths feed on the top through/wired to the other side of the 75 ohms and to the DAC's R&G&B negative signals.  Place as many of the decoupling caps on top to the sides of these signals.  Also, you should be using 0603 parts, or if your hands are steady enough,  go for 0402 for these DAC components so everything is in a straight line.

Under the dac, bottom layer, a fill GND should be used throughout.    Use 2 adjacent VIAs for every GND connection to the top layer.

For a 2 layer board, this should make a really good analog signal for your frequency range.

Remember, match red's return GND signal path with red's 75 ohm resistor, then to the dac's inverted red GNS input.  You do not want a signal reflection crosstalk across your video outputs since you didn't match GNDs.  The GND plane feeding the VGA connector's GND pins will be good enough for your bandwidth.

Made a start on the above - here's progress so far. Perhaps getting a little concerned about GND continuity, but not much I can do with that unless I start breaking signals or power lines out onto the bottom layer.

Close-up of the DAC area with a little more detail:

[BrianHG]

Excellent...

Push up C1, it is too close to the VGA plug.

Move up R2 and C2 closer to R1, lower U2 below C2.

You should now have a clear path for the Vaa on the top layer from regulator to all Vaa points since each GND should have their own vias by each component pad to the bottom layer.

Rotate the 3.3v regulator 90 deg. with it's caps allowing you to move the dac and vga plug a little further to the right so the have a little clearance from the fpga.

***********  Remember, the GND via for C5 and C3 should have their own via positioned closer to the DAC.  Those GND points should not have any other wires going out of them to the digital FPGA GND pins, or any other GND signals for the dac should not branch out to the fpga.


Everything else should work great.

[nockieboy]

Okay, here's the latest.  The blue area is the ground plane on the bottom layer.  Don't worry about the ratlines indicating I should connect up to FB3 and C47 underneath - I'm ignoring those and will probably amend the schematic to use a unique ground connection for the DAC components so I won't have to worry about the auto-router (if I ever use it again! ) connecting up the DAC ground to digital ground.

My only question is - where do I connect up the DAC ground plane? The nearest ground pin on the system header is at the top left of the 40-pin header next to the DAC.

[BrianHG]

Okay, here's the latest.  The blue area is the ground plane on the bottom layer.  Don't worry about the ratlines indicating I should connect up to FB3 and C47 underneath - I'm ignoring those and will probably amend the schematic to use a unique ground connection for the DAC components so I won't have to worry about the auto-router (if I ever use it again! ) connecting up the DAC ground to digital ground.

My only question is - where do I connect up the DAC ground plane? The nearest ground pin on the system header is at the top left of the 40-pin header next to the DAC.

(Attachment Link)

Pretty good.
Are your via's drill hole size large enough?
The 2 GND vias on the right of the dac are too close to the pins.  move those vias under the dac where you have space.  Same for the 2 GND vias at the top of the DAC.

You do not require a unique GND for your dac.  You do not require a ferrite bead for the FPGA PLL GND as well if you fill the bottom layer with a good GND.  Your bottom layer should be 95% GND fill for everything with a few opening voids for occasional power and signal traces.  It is just important that by the dac and it's regulator, that this GND section is 1 solid chunk without any voids for other traces.  What you have is good.

Note that a larger via server the equivalent to 2-3 of the finest possible vias.

Fill the Vaa between the right side of the DAC and U13 regulator and VGA plug so that the VaA trace is thick between C1 and the rest of the DAC.  make sure all your polygon clearances are something like 12mil, not 8 mil.  Too much copper fill close to pads make it hard to solder and are a continuous possible short point around drill holes.

[BrianHG]

Arrrg, 1 thing, rotate your entire 3.3v regulator section by 180 degrees...
Keep it's reference GNDs points as close to the DAC as possible and only allow in the dirty 5v at the outer edge of the design...

[nockieboy]

Are your via's drill hole size large enough?

They're all 12mil/24mil - standard size for EasyEDA (which I'm using to design the board) and JLCPCB's requirements.

[nockieboy]

Okay, latest update.  Just trying to manually route all the other lines now... and I'm starting to think I'll swap the 373s from the lower address lines for 245s, they'll make routing much easier even though I'll never need the ability to change the direction of the buffer.



Oh, I also noticed that I'd missed the HS and VS signals from the FPGA out!  I was wondering why I wasn't seeing ratlines from HS_IN and VS_IN on the line driver chip...  so that's eaten up another 2 IOs.

[BrianHG]

Well, if you have a problem with the VGA output quality, it will now be a software or VGA cable issue...

As for your 74HC logic, make the VCC & GND traces to the caps thick, like you have doe already for a few of them.
Remember that you do not need to wire GND-GND on each 74HC IC, just add 2 vias along the thick GND trace as it will meet with the GND flood fill on the bottom of the PCB.

As for the VCC, look for the most convenient path.  This may also be partially along the bottom edge of the PCB, coming to the top layer just by the first ICs.

[nockieboy]

 

Here's the PCB design - all manually routed.  I must admit, there's a certain sense of achievement in doing it yourself - plus much finer control over trace widths for power supplies etc. 

I get the feeling I've learned a lot from this exercise. 

 

[BrianHG]

Here's the PCB design - all manually routed.  I must admit, there's a certain sense of achievement in doing it yourself - plus much finer control over trace widths for power supplies etc. 

I get the feeling I've learned a lot from this exercise. 

 

Nice.       

Amazing job for a first timer!!!

Now, I understand the difficulty in achieving this 2 layer design with all the limitations.  Since I cant see net names, I only see 2 little things to consider.

FB4 is receiving power through a trace going through an IC pads and vias.  I'm not sure about the bottom cap next to how C10 is wired.  Try removing the FB3 and FB4 from your schematic.  You will simplify a few GND connections and remove a few caps in your design that way maybe allowing a better path for FB4's Vpll.

Hang on a sec, something seems wrong with the Vpll and VCCint, are some of those shorted, or, on the wrong pins?
Can you show me a printout/screenshot with net names on the FPGA pins?
As well as net names on the other components?

[nockieboy]

Hmm.. have PM'd you to see about giving you direct access to the project.  In the meantime, here's a breakdown of the design (one layer per page). Don't know if that will be useful?

[BrianHG]

The GND path under the FPGA and by the programming connectors is a little chopped up and can be easily fixed.  But, I want to look at the net names first as the Vpll and Vcore/int looks funny to me...

[nockieboy]

Okay, here's the latest on the schematic and PCB.  DRC completed with one error - the 5V line going up to R19 was only 10mil wide when the design rules called for 18mil, so I've widened that and there's no errors now.  I also moved the TCK trace up a little to hug around the NCONFIG via a little closer and make the underside look a little neater near the top. 

All I have to do now is wait for parts to arrive and order the PCB, once I'm absolutely happy I've got the right SD card socket (for some reason I'm finding it hard to get a matching part/footprint combination) and crystal oscillator package for the 50 MHz clock source.

 

[BrianHG]

DRC completed with one error - the 5V line going up to R19 was only 10mil wide when the design rules called for 18mil,

18MIL!!!
WTF, those pullups are 10kohm.  a 4 mil trace would have been overkill.

Anyways, take a look at the attached image, the trace circled in green it too wide for the pad.  Make it 12 mil.

[BrianHG]

If you decide to go with the CycloneIII on your next PCB, add this ram chip:

https://www.digikey.com/product-detail/en/cypress-semiconductor-corp/S70KS1281DPBHV020/2015-S70KS1281DPBHV020-ND/9955180

You only need 12 IOs & 1 PLL balanced Pos/Neg pair output set to 1.8v running at the core clock memory speed.  You'll get the full 16 megabytes MAGGIE can address on this 1 chip, though, you will need to mask out first 128kb for the onboard FPGA ram and you will may need to add a wait state when the Z80 reads this ram unless you are smart about the programming.  No DDR ram controller, just shift out an address and data, and wait for a response.

[nockieboy]

DRC completed with one error - the 5V line going up to R19 was only 10mil wide when the design rules called for 18mil,

18MIL!!!
WTF, those pullups are 10kohm.  a 4 mil trace would have been overkill.

Anyways, take a look at the attached image, the trace circled in green it too wide for the pad.  Make it 12 mil.
(Attachment Link)

  It didn't like the 10mil trace - I think because it was the only one on the board that was less than the 18mil minimum for the 5V net.

Have sorted that wayward trace on the FPGA too - thanks for spotting that. 

If you decide to go with the CycloneIII on your next PCB, add this ram chip:

https://www.digikey.com/product-detail/en/cypress-semiconductor-corp/S70KS1281DPBHV020/2015-S70KS1281DPBHV020-ND/9955180

You only need 12 IOs & 1 PLL balanced Pos/Neg pair output set to 1.8v running at the core clock memory speed.  You'll get the full 16 megabytes MAGGIE can address on this 1 chip, though, you will need to mask out first 128kb for the onboard FPGA ram and you will may need to add a wait state when the Z80 reads this ram unless you are smart about the programming.  No DDR ram controller, just shift out an address and data, and wait for a response.

I like the look of that.  Could be a good (inexpensive) introduction to BGA soldering for me...

[BrianHG]

If you decide to go with the CycloneIII on your next PCB, add this ram chip:

https://www.digikey.com/product-detail/en/cypress-semiconductor-corp/S70KS1281DPBHV020/2015-S70KS1281DPBHV020-ND/9955180

You only need 12 IOs & 1 PLL balanced Pos/Neg pair output set to 1.8v running at the core clock memory speed.  You'll get the full 16 megabytes MAGGIE can address on this 1 chip, though, you will need to mask out first 128kb for the onboard FPGA ram and you will may need to add a wait state when the Z80 reads this ram unless you are smart about the programming.  No DDR ram controller, just shift out an address and data, and wait for a response.

I like the look of that.  Could be a good (inexpensive) introduction to BGA soldering for me...

That 1mm pitch BGA and the 240 pin QFP is your only solution for a 2 layer PCB with ram and no DRAM controller to engineer.  Every other option requires 4 layers and the lattice requires 10 or 8 mil vias because of it's density.

[nockieboy]

That 1mm pitch BGA and the 240 pin QFP is your only solution for a 2 layer PCB with ram and no DRAM controller to engineer.  Every other option requires 4 layers and the lattice requires 10 or 8 mil vias because of it's density.

I'd be happy to give that a try.  Once I've got a working v1, seems like the Cyclone 3 would be a worthwhile step up - it's significantly bigger than the CE4 chips though and will leave me with some routing headaches, I suspect, to cram it all into the form factor I'm working with.

[BrianHG]

That 1mm pitch BGA and the 240 pin QFP is your only solution for a 2 layer PCB with ram and no DRAM controller to engineer.  Every other option requires 4 layers and the lattice requires 10 or 8 mil vias because of it's density.

I'd be happy to give that a try.  Once I've got a working v1, seems like the Cyclone 3 would be a worthwhile step up - it's significantly bigger than the CE4 chips though and will leave me with some routing headaches, I suspect, to cram it all into the form factor I'm working with.

No it wont.  All those extra IO means mostly single file traces next to each port.  With a lot of blank IO pins.

[nockieboy]

The EP4CE10E22C8N arrived today - I notice it has a ground pad underneath the body of the chip, which the part doesn't have in EasyEDA.  I've checked the Intel literature and yes, the EP4CE10E22 DOES have a ground pad and it's supposed to be connected to GND, so I'll need to update the PCB design with this.

Here's what's got me thinking, though - how do I solder that central pad under the chip to GND?  I suppose I could place a few large vias there and use a hot air gun to heat the PCB up from the underside? Any suggestions?

[BrianHG]

You can fake place a GND pad for the open copper area.  (IE, create a new custom home made SMD component with 1 pad connected to GND.)  A number of vias to GND within the pad around the perimeter will also be needed.  But, I recommend searching for the correct footprint type as it a standard and such a component will have the proper paste stencil.

As for soldering, hot air will do, baking is better but I know you are hot properly setup for that.

[nockieboy]

Okay, well it looks like the pad in the footprint I'm using is a little larger than the actual ground pad on the IC, and I'd just finished the attached update to the PCB before I read your post about putting vias around the edge - hopefully this will be alright?  I've moved the 2.5 line on the bottom side down, so it goes around the edge of the centre of U1 and there's now a nice ground plane under U1.

[BrianHG]

Okay, well it looks like the pad in the footprint I'm using is a little larger than the actual ground pad on the IC, and I'd just finished the attached update to the PCB before I read your post about putting vias around the edge - hopefully this will be alright?  I've moved the 2.5 line on the bottom side down, so it goes around the edge of the centre of U1 and there's now a nice ground plane under U1.

Everything looks good.
You still haven't considered the additional GND connections on the edge connectors which I mentioned earlier.