FPGA VGA Controller for 8-bit computer

[nockieboy]

Oh crap, I've lost count on how many times did I make the same mistake!

It really shouldn't make me feel better, but knowing I'm not the only one who makes these mistakes does make me feel like I should be less harsh on myself. 

[nockieboy]

Little length and matching cleanup.  We are assuming that this matches the length from the IO pins on the eval board below.  The goal is at the end where the 100ohm termination resistors are located, the overall length of the +&- tracks are identical.

We cant do anything about the differences through the connector itself, only correct after the connector so it will undo the length difference introduced before the first connector on the bottom.

So you mean correct for any differences in length created on the EasyFPGA board itself? 

[BrianHG]

Uhh that was a silly mistake with the header - I don't know if it was an issue with the type of header I'd used or what, but it was clearly wrong - well done for spotting that one.

Have updated the schematic and PCB with the other changes - should be up to date so far. 

Why cant my Adobe reader see your schematic.  It says I need a font package.
I don't like downloading unknown addons or upgrading to spy-ware...

[BrianHG]

Little length and matching cleanup.  We are assuming that this matches the length from the IO pins on the eval board below.  The goal is at the end where the 100ohm termination resistors are located, the overall length of the +&- tracks are identical.

We cant do anything about the differences through the connector itself, only correct after the connector so it will undo the length difference introduced before the first connector on the bottom.

So you mean correct for any differences in length created on the EasyFPGA board itself? 

Follow my picture.  The traces are going to the same pins, just that they run vertical before the +&- go into their 50ohm parallel routing.  The EasyFPGA looks like it takes a similar vertical route from IO pin to the connector.  We are just following the same parallel vertical trace flow and by the time the 2 traces go parallel on your HDMI PCB, the difference in length should be ~cancelled out.

[nockieboy]

Why cant my Adobe reader see your schematic.  It says I need a font package.
I don't like downloading unknown addons or upgrading to spy-ware...

Oooh... no idea? I've not changed any fonts in it or anything.  It was using Times New Roman and Verdana... Hmmm.. try this one?

[asmi]

It really shouldn't make me feel better, but knowing I'm not the only one who makes these mistakes does make me feel like I should be less harsh on myself. 

It just shows that we all are human beings, and so we all make mistakes. Which is why I always say (including to myself) - "Wait one more day and check everything one more time". Unfortunately I rarely listen to myself as whenever I complete a layout, I get so excited that I want to order PCBs ASAP , and that backfires on me every once in a while, especially often on "revision A"'s

[BrianHG]

Why cant my Adobe reader see your schematic.  It says I need a font package.
I don't like downloading unknown addons or upgrading to spy-ware...

Oooh... no idea? I've not changed any fonts in it or anything.  It was using Times New Roman and Verdana... Hmmm.. try this one?

This is what I see:

Though Firefox shows it ok (crummily), though Firefox renders & prints .pdfs like crap.

[nockieboy]

I use Foxit Reader to view PDFs - both on the desktop and (I think) in browsers.  Here's what it should look like:

[asmi]

Here I can open both with Adobe Acrobat Reader and both look OK.

[nockieboy]

Little length and matching cleanup.  We are assuming that this matches the length from the IO pins on the eval board below.  The goal is at the end where the 100ohm termination resistors are located, the overall length of the +&- tracks are identical.

We cant do anything about the differences through the connector itself, only correct after the connector so it will undo the length difference introduced before the first connector on the bottom.

So you mean correct for any differences in length created on the EasyFPGA board itself? 

Follow my picture.  The traces are going to the same pins, just that they run vertical before the +&- go into their 50ohm parallel routing.  The EasyFPGA looks like it takes a similar vertical route from IO pin to the connector.  We are just following the same parallel vertical trace flow and by the time the 2 traces go parallel on your HDMI PCB, the difference in length should be ~cancelled out.

Ah - the picture wasn't there when I looked.  How about this now?  I've removed the top silk mask to show the traces better.

[BrianHG]

beautiful  .
Time to start coding...

Let's start by dismantling everything but the sync generator & driving the existing VGA output on that PCB with 3bit color pattern.

Then, we will need 2 pieces for the HDMI.  (I still need to check something...)

Module #1: Clk, clk_ena, 24bit RGB +HS+VS+DE input, 4x10 bit parallel output.
This module takes in the VGA parallel interface and outputs 3x10bit parallel data which contains the 3x RGB channels with the embedded/encoded sync information.  Channel #4 is actually a fixed # "10'b1111100000" as it generates the pixel clock out.

Module #2: This will be an Intel megafunction which takes in the pixel Clk, Clk_10x which will be the serial output clock, and the 4x channels from module #1.  It will output 4 parallel serial streams which will feed the LVDS output butters.

That should make a DVI picture.

Then we will advance module #1 to add embedding audio packets during the horizontal blanking interval.
(Need to double check how this works.)

There are also concerns about HDMI being forced into YUV color mode instead of RGB, though RGB supposed to be supported.  I have numerous RGB to YUV color space converters, though I would like to avoid this step.  (You would get brightness, contrast, saturation and hue controls on your video card if you added the color-space-converter...)

[mariush]

The PDF includes a font called Simhei : https://www.wfonts.com/font/simhei

As for that schematic, is it acceptable to have those center trace pairs shorter in length compared to the ones on the side?

Also nitpicking, but personally it would bother me that single trace on top right of the connector going around the last trace.
It seems possible to route it along the other two to its left, pull those a bit closer to the chip at the corner and maybe place that capacitor or whatever it is diagonally? Horizontal would also work, just route that single trace on the right between the capacitor pads?

Maybe I'd thicken the trace going to the 2nd set of two pins on the 0.1" header a bit.

[BrianHG]

Also nitpicking, but personally it would bother me that single trace on top right of the connector going around the last trace.

It's the opposite orientation of what the length and trace spacing looks like on the PCB below with that yellow connector.  All we are trying to do is un-do that extended length of trace on the bottom PCB which would be on the opposite pin.

You would be absolutely correct in your judgement if the bottom PCB had matched the length of the traces to the differential paired IO pads on it's din connector.  This is not the way our real PCB will be wired straight to the BGA FPGA.  We are just best accommodating the cheap 25$ eval board to test out the NXP HDMI/DVI amplifier / cable driver IC.

(Note that the PCB is rotated around 180 degrees before being plugged in, so the lengths between the upper and lower pins to the FPGA equalize out  It's the parallel differential 100ohm terminator which need to be dead center at the end of the balanced trace pair and they are the way it's wired.)

[nockieboy]

Owzat?

And what BrianHG said re: trace matching. 

[BrianHG]

Owzat?

And what BrianHG said re: trace matching. 

Nockieboy, you didn't have to do that change, mariush could have not possibly been talking about the DDC and HPD lines.  These signals operate at 100KHz.  You could run circles around the PCB going through each layer and it would still work.

[nockieboy]

Nockieboy, you didn't have to do that change, mariush could have not possibly been talking about the DDC and HPD lines.  These signals operate at 100KHz.  You could run circles around the PCB going through each layer and it would still work.

Yeah, I know, but I have a bit of OCD when it comes to fine-tuning stuff like this.  I could happily spend the next week tweaking signal traces and component positioning to make it as efficient as possible (within my level of skill and knowledge, obviously).

[asmi]

Module #2: This will be an Intel megafunction which takes in the pixel Clk, Clk_10x which will be the serial output clock, and the 4x channels from module #1.  It will output 4 parallel serial streams which will feed the LVDS output butters.

Are you sure you will need a 10x clock? On Xilinx devices output SERDES operates in DDR mode, so it only requires 5x clock (because DDR). So for 720p you only need 371.25 MHz for the pixel clock as opposed to 742.5 MHz. This is why it's possible to achieve 720p while being completely in spec (global clock buffers can only go up to 630 MHz or so).

[asmi]

Yeah, I know, but I have a bit of OCD when it comes to fine-tuning stuff like this.  I could happily spend the next week tweaking signal traces and component positioning to make it as efficient as possible (within my level of skill and knowledge, obviously).

If I were you, I'd rather look at the 3D model of the board with all parts on there and see if I can actually hand-assemble it. For example, the passive connected to the right bottom pin of that QFN looks to me a bit too close to the QFN to actually solder it with an iron without touching the QFN. Try to think about the order in which you will be soldering parts and see if something might be in the way of a soldering iron at some point in assembly.
I assume you are going to hand-solder it, if not, pls ignore everything I just said.

Also, just in case you guys didn't see it first time around, I would like to once again suggest going for 0.8 mm thick board as opposed to regular 1.6 mm. This should lower trace impedance and bring it a bit closer to 50 Ohm as they are supposed to be.

Oh, and one more thing - if you will be OK with 24/25 Hz refresh rate as opposed to 60 Hz, you can do full 1080p with the same bandwidth (or slightly lower for 24 Hz) as 720p@60.

[BrianHG]

Module #2: This will be an Intel megafunction which takes in the pixel Clk, Clk_10x which will be the serial output clock, and the 4x channels from module #1.  It will output 4 parallel serial streams which will feed the LVDS output butters.

Are you sure you will need a 10x clock? On Xilinx devices output SERDES operates in DDR mode, so it only requires 5x clock (because DDR). So for 720p you only need 371.25 MHz for the pixel clock as opposed to 742.5 MHz. This is why it's possible to achieve 720p while being completely in spec (global clock buffers can only go up to 630 MHz or so).

Yes, 2:1 and 1:1 modes exist.  In 2:1 DDR mode, 840mb, IE:420Mhz is the peak for a -C6 grade device.  Oddly, in 1:1 mode, you can clock an IO up to 500MHz, IE, maximum toggle rate of 250Mhz on a single clocked DFF driving an IO pin.  I wonder if this means a low quality out of spec 1gb/sec might be possible in DDR mode.

[BrianHG]

Oh, and one more thing - if you will be OK with 24/25 Hz refresh rate as opposed to 60 Hz, you can do full 1080p with the same bandwidth (or slightly lower for 24 Hz) as 720p@60.

Well, 30Hz... Forgot about that one, but yes, 30Hz 1080p can be done if 720p works. (Including 24Hz & 25Hz)

That would be nice to see a Z80 playing 1080p games even it the frame-rate is 30Hz....

You got the ram for it.
But, with a fill rate of around 75million pixels a second, except for tile-constructed playfields and use of sprites, or just huge stored bitmaps, maintaining 30fps gaming can get difficult.

[nockieboy]

Yeah, I know, but I have a bit of OCD when it comes to fine-tuning stuff like this.  I could happily spend the next week tweaking signal traces and component positioning to make it as efficient as possible (within my level of skill and knowledge, obviously).

If I were you, I'd rather look at the 3D model of the board with all parts on there and see if I can actually hand-assemble it. For example, the passive connected to the right bottom pin of that QFN looks to me a bit too close to the QFN to actually solder it with an iron without touching the QFN. Try to think about the order in which you will be soldering parts and see if something might be in the way of a soldering iron at some point in assembly.
I assume you are going to hand-solder it, if not, pls ignore everything I just said.

Also, just in case you guys didn't see it first time around, I would like to once again suggest going for 0.8 mm thick board as opposed to regular 1.6 mm. This should lower trace impedance and bring it a bit closer to 50 Ohm as they are supposed to be.

Oh, and one more thing - if you will be OK with 24/25 Hz refresh rate as opposed to 60 Hz, you can do full 1080p with the same bandwidth (or slightly lower for 24 Hz) as 720p@60.

It all looks okay to my untrained eye?  The HDMI connector is an approximation - there's no 3D model for one I'm using.

And yes, I saw the 0.8mm board recommendation and will be using that when I place the order.

[asmi]

It all looks okay to my untrained eye?

Yea, those are seriously large pads for QFN - I did not expect that. I don't see orientation mark for the QFN on a silkscreen - but maybe it's just a bad angle.
I would work a bit on a silkscreen, but layout-wise it looks OK to me, at least on the first sight.

[BrianHG]

I don't see orientation mark for the QFN on a silkscreen - but maybe it's just a bad angle.
I would work a bit on a silkscreen, but layout-wise it looks OK to me, at least on the first sight.

Yes, the pin 1 ID is missing...
Add a fat dot or arrow on the silkscreen.

[BrianHG]

Well Nockieboy, if you got your blitter emulated text mode fully functional, then, at 1920x1080, you can render a nice high resolution 24x36 pixel font roasting the old 8x16 and still get 80 column x 30 rows, or use a 20x36 font so the text still looks square on a 16:9 display with 96x30 characters.  In fact, you have enough ram for a 2 bit 4 color font where you can dither the edges to 2 additional shades of grey plus the white or 16 color fonts with 14 shades of grey plus the white text.

[asmi]

Yes, the pin 1 ID is missing...

I don't see polarity mark for the diode either.