FPGA with two DDR2/3 PHY and free dev tools

[Boscoe]

Hi all,

I’ve been looking through the Xilinx and Intel websites trying to find an FPGA as above. I have two data streams in my project would rather not have to design a build a method for them to share the same memory. Anyone know of any parts? A dev board with reference design would be magic!

Thanks
Boscoe

[apblog]

I can't help you with your actual question.

But it's super easy to share 1 DDR controller between two or more IP blocks.  With Xilinx, I would use a Zynq that has a hard memory controller, and connect to it with an AXI DMA IP block, 1 for each stream.

You can do the same thing in Artix too, with the Memory Interface Generator.

[asmi]

Seriously? Using Zynq with all complexities that it brings, only for memory controller?

To OP: 7 series FPGAs from Xilinx allow implementing any number of independent DDR2/3 controllers - as long as you have enough IO pins to physically implement interfaces.

[nctnico]

Hi all,

I’ve been looking through the Xilinx and Intel websites trying to find an FPGA as above. I have two data streams in my project would rather not have to design a build a method for them to share the same memory. Anyone know of any parts? A dev board with reference design would be magic!

On Spartan6 you can have multiple memory interfaces to the same memory which then get multiplexed onto the physical interface towards the memory. Works like a charm. Do keep in mind that DDR memory has some variable latency so you'll need some (FIFO) buffering if you want to store a continuous stream of data.

Another option is to use an internal adres/data bus which has the memory mapped into a certain area. The bus arbiters can then take care of concurrent data transfers to and from the memory. In one of my designs I used 2 memory interfaces and mapped the same memory into the memory map twice at different addresses. This allows for two devices to access the memory simultaneously without giving up any flexibility.

[apblog]

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