A Lattice FAE can help with your exact problem. Meanwhile this VHDL example might be useful. It runs the PLL at 500 MHz from a 24MHz input clock. CLKOS is 250MHz (i.e. 500/2) which is then divided down by 10 in the feedback path. The fractional divider, also in the feedback path, drops 25MHz to 24MHz so that the loop locks.
-- 25/24 = 1.041666 = 1 + 0.041666 = 1 + 2731/65536
FRACN_DIV => 10 * 2731, -- 25MHz down to 24MHz
FRACN_ENABLE => "ENABLED",
CLKOS_DIV => 2, -- 500MHz PLL -> 250
CLKI_DIV => 1,
CLKFB_DIV => 10, -- 250MHz from DivB/ClkOS -> 25
FEEDBK_PATH => "INT_DIVB",
This only makes sense in conjunction with the PLL diagram in the Lattice TR, and even then it isn't super-clear.