Free softcores usage: XILINX x ALTERA

[andre_teprom]

Hi there,


I wish know about opinions from persons who already have experienced both ALTERA and XILINX manufacurers’s IP softcores and their related free tools.
I’m not exactly referring to placing the HDL of some of the various open cores available on the Web, but I’m rather interested on the manufacturer toolsets, including not only the core itself, but also their peripherals.

In my particular case, I’ve been making experiments with the Altera Cyclone II with the NIOS2, and although I liked a lot, as well got some successful results, I found it’s usage a little difficult, but once I never used the XLINX concurrent, MicroBlaze, I’m obviously unable to assess which one is more friendly or not.

So, could someone give me some remarks ?

[nctnico]

Lattice has the LM32 core which is also nice and completely free to use with any kind of FPGA.

[andre_teprom]

I appreciate a lot your prompt reply, however irrespective to the attributes of Lattice's cores as well as its portability to other platforms, I was more interested solely on Altera and Xilinx brands due to the fact that these manufacturers are comparatively somewhat more popular among designers - therefore, being easiest to get support on the comunity.

Anyway, my focus of interest was regarded to the tools provided by these manufacturers. For instance, with the Altera's Qsys and NioS2 we're able to setup a new design with friendly user interfaces, but I don't know anything about the Xilinx.

[jeremy]

I can't help you wrt the soft cores, but I have used Vivado with the Zynq processors which have a hard ARM core and a similar IDE process to using the microblaze (i think). Like most FPGA tools, it's a pretty steep learning curve and there are some strange idiosyncrasies, but as far as them being usable pieces of software I think Qsys and Vivado are about equal. If you plan on using older Xilinx chips beware though, as Xilinx are refusing to support any chips before the 7 series in Vivado, and instead forcing you to use ISE.

I think also an important thing is whether you have logic debug cores available. iirc Altera has it for free, whereas only 7 series Xilinx chips get it for free (because it only became free in Vivado). If you're using a Stratix 10 or something though, I suppose license fees are the least of your worries

[nctnico]

I appreciate a lot your prompt reply, however irrespective to the attributes of Lattice's cores as well as its portability to other platforms, I was more interested solely on Altera and Xilinx brands due to the fact that these manufacturers are comparatively somewhat more popular among designers - therefore, being easiest to get support on the comunity.

Anyway, my focus of interest was regarded to the tools provided by these manufacturers. For instance, with the Altera's Qsys and NioS2 we're able to setup a new design with friendly user interfaces, but I don't know anything about the Xilinx.

One hint I can give you is to also look at how you can identify the peripherals in run time. The LM32 core has a Wishbone interface. Part of the Wishbone interface are crossconnects which can also contain a map of the connected peripherals. Since these crossconnects can be cascaded you can als traverse through the peripherals. The end result is that you only need to know the address of root peripheral map in order to find the addresses of all the peripherals through a unique ID. This method allows the hardware designer to re-arrange the entire memory map without the firmware needing to know about it. IMHO this is a pretty strong point of the Wishbone architecture because it means the hardware and firmware engineers have one item less to discuss and document.

[andre_teprom]

One hint I can give you is to also look at how you can identify the peripherals in run time. The LM32 core has a Wishbone interface. Part of the Wishbone interface are crossconnects which can also contain a map of the connected peripherals.

As far as I know, Altera already has the same feature with the Avalon bus. The addres's re-mapping should be updated after some change in the interconnects, or addition/removal of peripherals.

Do you have been used both manufacturer’s tools so that could provide your ‘particular’ opinion regarding to how friendly is each one ?

I liked a lot the Quartus/Qsys/Nios2 toolset, but sometimes I find them as being more like separated tools working together than properly as part of an integrated environment. It is not rare to spend a lot of time to solve simple issues not related to the design itself, but to some mismatch at the tool.

At this exact moment, I’m planning to purchase a more sophisticated Development Kit than the Cyclone II based board that I bought just for taste, but for while I’m not concerned on performance neither in relative cost per resources, but the criteria that I’ll adpt to decide is the time to develop.

[nctnico]

So far I have only used the LM32 core in a complex Spartan6 project without any (fancy) GUI tools. I just attach the peripherals using VHDL code.

[Scrts]

I've only worked with Microblaze on Spartan-3E, but it was not free by the time. Did they introduce free Microblaze (not Picoblaze) since?

I am happy with Nios II/e, which is free and works great. Many of Nios systems were made to hardcore. E.g. Altera DDR3 PHY initialization is done by hardcored Nios.