Gowin B-SRAM Bit Ordering

[gnuarm]

i want to use a 2 port B-SRAM as an interface between two processes with different bit widths.  One port should be 1 bit wide and the other port should be 16 bits.  I can't find anything saying which bit in the 16 bit words maps to which sequence of addresses in the 1 bit port. 

This is sort of a big endian vs. little endian thing, I can see either connection being justified.  I'm rather hoping it is little endian with the lsb of the 16 bit words mapped to addresses xxx0 and the msb mapped to xxxF. 

I'm only asking here because I don't know of any forums where Gowin devices are much discussed.  if no one knows I guess I can rig up a simulation and test it out.  That will be another module I'll have to reverse engineer as any detailed documentation is pretty much absent.  Or I could ask the FAE.  He seems to be a pretty good guy and so far doesn't seem to mind my questions.

[BrianHG]

You can simulate and test.  Usually 0x0 would point to the LSB of the 16 bit side while 0xF would point to the MSB as you are basically addressing in order of magnitude, however, this is what I have used in Intel's Quartus.

If you want to change the order, you can XOR your address on the chosen side of the ram with 0x00F.
Or, swap the bits around on the 16 bit side.
There is 0 delay or logic consumption in doing so in an FPGA.

Worst case, you can do 16bit x 16bit and demux the output / or use a bit write mask to write 1 bit at a time.

(Additional note: in some of my code, I just have a 'parameter' to select the endian...)

[SiliconWizard]

If this is not documented, this clearly sucks. I guess you could safely assume this will be LSB first, as this is how it's done one most FPGAs I know of these days, but this *should* be documented by GOWIN. Is there no doc for this? And yes, in doubt, just test it. Or use the same width on both ports and do the serializing or deserializing yourself, which is not hard.