generate SPI in verilog

[ali_asadzadeh]

Hi,
I have a 16Bit SPI master and I need to generate 9 of them,

Here is my code

Code: [Select]

wire wStart , wAdcDv;
wire [15:0] wAdcData [8:0];

// The for-loop creates 9 ADC statements
genvar i;
generate
for (i=0; i < 9; i = i + 1) begin
SPI_Master SPI(
.i_Clk(i_Clk50MHz),
.i_Rst(1'b0),
.i_start(wStart),
.o_RXData(wAdcData[i]),
.o_DV(wAdcDv),
.o_Busy(),
//physical pins
.i_MISO_pin(i_AdcSdo[i]),
.o_SCLK_pin(o_AdcSck[i])
);
end
endgenerate

ISE would complain about

Signal o_AdcSck[8] in unit top is connected to following multiple drivers

What am I doing wrong?

[dtodorov]

Not sure if it can help, but maybe you can try to explicitly define

Code: [Select]

wire [8:0] o_AdcSck;


[BrianHG]

ISE would complain about

Signal o_AdcSck[8] in unit top is connected to following multiple drivers

What am I doing wrong?

Usually this means that somewhere else in your code, you have set or assigned 'AdcSck[8] <=' to something.  You cannot set 2 different values to the same IO pin or logic cell.

[ali_asadzadeh]

Usually this means that somewhere else in your code, you have set or assigned 'AdcSck[8] <=' to something.  You cannot set 2 different values to the same IO pin or logic cell.

Thanks, Stupid me, I have some typo in somewhere else

[BrianHG]

Usually this means that somewhere else in your code, you have set or assigned 'AdcSck[8] <=' to something.  You cannot set 2 different values to the same IO pin or logic cell.

Thanks, Stupid me, I have some typo in somewhere else

Been there, done that who knows how many times.
Also, it took a few times seeing that same error message in Quartus before I knew what to look for every time it shows up.