according to my tests, it has about 200-500 ps with no use PLL. Unfortunately I don't have equipment to measure it precisely, but I know that it is much worse than 100 ps. Other peoples have the same experience.

I can give you an idea. Attach two separate oscillators to the FPGA. Forward one out of FPGA, connect it externally to a different pin, and sample it with a clock from the other oscillator. Since the oscillators are a little bit different in the frequency, one will be slipping relative to the other. There will be a long period of '1' then a long period of '0', then '1' again etc.

If there were no jitter, the transition would be momentary - you get '1', and then you get '0'. However, because of the jitter, there will be a transitional period - where '1' and '0' are mixed. You just record the length of the transitional period Tt. And you compare it to the full cycle Tc. Then, you calculate the estimate of jitter:

J = P * Tt/Tc

where P is the clock period and J is the jitter.

For example, you have two 50 MHz clock sources. If they are 10 ppm, say one is 50.0005 MHz and other is 49.9995 MHz. So, the fast one will outpace the slow one by the whole cycle in approximately 1/(50.0005 - 49.9995) = 1 ms (if you're lucky, this may be much longer giving you better resolution). Say, you detected the period where '1' and '0' were mixed which lasted 250 samples = 5 us. Then you have:

Tc = 1 ms = 1000000000 ps

Tt = 5 us = 5000000 ps

P = 20 ns = 20000 ps

J = 20000 * 5000000 / 1000000000 = 100 ps

If the period is longer than 250 samples, the jitter is more than 100 ps. If the period is less than 250 samples, the jitter is less than 100 ps.

Then you repeat the experiment, but take the FPGA output out of the loop - you enter one oscillator as data into FPGA and sample it with the clock from the second oscillator. This way, you get jitter value without FPGA involved - J0. Then you calculate how much jitter can be attributed to the FPGA:

Jfpga = sqrt(J^2 - J0^2)

Similarly you can test your logic ICs and various frequencies.

All you need is an FPGA board with footprints for 2 different MEMS. This would seem to be a common thing, but I looked through all mine and I haven't found any.