Generating a 600KHz clock with 10ps Jitter

[ali_asadzadeh]

Hi,
I have used AD9517-3 in a ZYNQ project before, Now I have a new project, which I need to sample a low speed ADC with 600KHz sample clock, but the problem is that, my customer needs a maximum 10ps jitter sample clock. I told them I will use AD9517 with the fs jitter, But I will divide the generated clock inside the FPGA to achieve the low speed clock with low jitter. But they told me they had a problem with this Technic and spartan 6 before, the Flip-flops inside the FPGA and in the last stage will determine the over all jitter, and they would add so much jitter (in the range of 100-200ps) to the generated clock. so do we have a way of creating a low speed clock with low jitter?

[Kleinstein]

One could add an additional external sync stage outside the FPGA, so another last flip-flop with a suitable low jitter clock (before the divider / PLL). It depends on the clock if this is possible.

[ejeffrey]

Yeah, running through an FPGA will definitely introduce jitter.  How much depends on exactly how you do it and which pins and IO standard you use.  Furthermore, there will be a static propagation delay that depends on the compilation, so if you need the timing to be constant even under updated bitstreams that adds another level of problem.

If you need to use the FPGA to produce the clock for some reason you can use an external D flip flop clocked by your high speed clock to generate a low jitter version.  Alternately just use a discrete clock divider.

[ali_asadzadeh]

Yeah, running through an FPGA will definitely introduce jitter.  How much depends on exactly how you do it and which pins and IO standard you use.  Furthermore, there will be a static propagation delay that depends on the compilation, so if you need the timing to be constant even under updated bitstreams that adds another level of problem.

If you need to use the FPGA to produce the clock for some reason you can use an external D flip flop clocked by your high speed clock to generate a low jitter version.  Alternately just use a discrete clock divider.

The clock generation inside the FPGA is not a must, reading the ADC and doing some DSP on it, should be done in the FPGA, so I thought generating the clock inside the FPGA would ease the problem, the Sample clock should be adjustable, so I thought I could use FPGA and the external AD9517 to achieve the desired clock frequency, But if it can not be done in the FPGA, I can use external parts, what discrete solution or parts do you suggest?

[BrianHG]

Furthermore, there will be a static propagation delay that depends on the compilation, so if you need the timing to be constant even under updated bitstreams that adds another level of problem.

It's possible to tell you FPGA compiler to use the IO pin's dedicated flipflop register which would guarantee pin timing every build no matter the logic.  This exists usually for the DQ pins for DDR/QDR memory IO pins as their timing is crucial when operating above the 1GHz range.

If you use a SERDES pin in the serdes mode to drive your clock output, especially if the FPGA has 12/25GBps outputs, the timing constraints do improve vastly and will be guaranteed every compile as well.

However, I don't believe the OP will be using a 2-20K$ FPGA for a 600Khz clock.

+1 on using just an external D-flipflop with picosecond jitterles output while using the FPGA to feed it's data input, and using the flipflop's data out as your clock.  Obviously the D-flipflop clock input would share the AD9517-3 clock output with the FPGA.

[ali_asadzadeh]

I'm intended to use this puppy,XC7Z020-2CLG400I  also I have already told you the clock chip, But I can change the clock chip, so I could achieve my desired goal, so what do you suggest then?

[Marco]

What's wrong with Kleistein's suggestion? Do clock division inside the fpga and add a single external logic IC to reallign it with the undivided low jitter clock.

Just need to make sure the edges aren't too close together to keep it deterministic.

[ali_asadzadeh]

Is this clock generator satisfying? si5391 from silicon labs, it has fs jitter spec and can produce from 100Hz to 750MHz, but the jitter is only specified for some frequencies (in the 100 to 200MHz! is it any good for 600KHz?

[NorthGuy]

The least jitter you can get is by feeding the original clock to a clock-capable pin, and use two ways - (a) to produce the divided signal, and (b) to feed BUFIO which will clock the final stage (e.g. OSERDES or ODDR) forwarding the divided signal to the outside. Whether this would be good enough for you, hard to tell.

[Marco]

AFAICS you want pll bypass if you really want to use a synthesizer, you just need to divide a 48 MHz crystal clock by 80.

[ali_asadzadeh]

AFAICS you want pll bypass if you really want to use a synthesizer, you just need to divide a 48 MHz crystal clock by 80.

The jitter is my main concern! the Si5391 claims it can do it, my customer has negative feedback on the use of FPGA, it would add jitter in the range of 100-200ps, have you done it before?

[Marco]

No, but I can think logically. A PLL/VCO is an unknown, it will never improve over the longer time scale stability ... why seek trouble?

So if you want to use a synthesizer, pick another one with PLL bypass.

[BrianHG]

     That 10ps jitter spec on a 600KHz sampling clock.  Never mind the AD9517 PLL, but, do you have the skills and background to make a PCB, surrounding support circuitry and shielding required to achieve this specification?  (IE: ensure that the AD9517 PLL you are using will not receive any external interference at any time diminishing it's jitter performance)  Do you have the appropriate testing hardware to prove you have met this specification.  Do you know the price of such test instruments which may be used to confirm this specification as such instruments would require sampling clock circuitry with jitter in the sub-picosecond range.

     No insult intended, but, if I was told I had to guarantee 10ps jitter, I could not do so without the test hardware to back up my claim.  I cannot have my client come back to me a year later with a lawsuit for millions lost in revenue due to a portion of their PCBs having 11ps jitter on their 600KHz clock.

[BrianHG]

Good Luck:
https://www.idt.com/us/en/products/clocks-timing/jitter-attenuators-frequency-translation/8t49n240-femtoclock-ng-universal-frequency-translator

[ali_asadzadeh]

     That 10ps jitter spec on a 600KHz sampling clock.  Never mind the AD9517 PLL, but, do you have the skills and background to make a PCB, surrounding support circuitry and shielding required to achieve this specification?  (IE: ensure that the AD9517 PLL you are using will not receive any external interference at any time diminishing it's jitter performance)  Do you have the appropriate testing hardware to prove you have met this specification.  Do you know the price of such test instruments which may be used to confirm this specification as such instruments would require sampling clock circuitry with jitter in the sub-picosecond range.

     No insult intended, but, if I was told I had to guarantee 10ps jitter, I could not do so without the test hardware to back up my claim.  I cannot have my client come back to me a year later with a lawsuit for millions lost in revenue due to a portion of their PCBs having 11ps jitter on their 600KHz clock.

Thanks, i do not have the test hardware, But hopefully the client had it! so I can test it for free in their lab.
Thanks for the IDT link though, I have saw that, But I think silicon labs part, Si5340 is easier to work with. Also in page 11 of this IDT device it told that the minimum output clock is around 15.25MHz with the maximum Div setting.

[BrianHG]

     That 10ps jitter spec on a 600KHz sampling clock.  Never mind the AD9517 PLL, but, do you have the skills and background to make a PCB, surrounding support circuitry and shielding required to achieve this specification?  (IE: ensure that the AD9517 PLL you are using will not receive any external interference at any time diminishing it's jitter performance)  Do you have the appropriate testing hardware to prove you have met this specification.  Do you know the price of such test instruments which may be used to confirm this specification as such instruments would require sampling clock circuitry with jitter in the sub-picosecond range.

     No insult intended, but, if I was told I had to guarantee 10ps jitter, I could not do so without the test hardware to back up my claim.  I cannot have my client come back to me a year later with a lawsuit for millions lost in revenue due to a portion of their PCBs having 11ps jitter on their 600KHz clock.

Thanks, i do not have the test hardware, But hopefully the client had it! so I can test it for free in their lab.
Thanks for the IDT link though, I have saw that, But I think silicon labs part, Si5340 is easier to work with. Also in page 11 of this IDT device it told that the minimum output clock is around 15.25MHz with the maximum Div setting.

The are 2 banks of outputs.  The fast ones for the high frequency, multiple outputs and the slower one.  See what the 'fractional' divider for that port can do can do.

[NorthGuy]

But hopefully the client had it! so I can test it for free in their lab.

Then you can test the jitter introduced with FPGA. Connect the original clock to a clock-capable pin, then feed BUFIO, then forward the clock out with ODDR (google "clock forwarding" if you don't know how to do it).

Certainly, PLL and other clock managing things inside FPGA would introduce jitter. So, your client didn't like it. The tiny BUFIO loop may introduce some jitter too, but certainly not as much as PLL. It might be Ok for you.

[SiliconWizard]

Wouldn't testing < 10ps jitter require some serious lab equipment?

[Marco]

Is the jitter of even the lousiest 48 MHz crystal over 80 cycles going to get near a single ps? I kinda doubt it.

[dmills]

As to measuring such things, measure phase noise instead...

Build two of em, lock them in quadrature then a mixer, low pass filter and a low frequency spectrum analyser (Sound card for the close in stuff), turning phase noise into RMS jitter is annoying maths, but it is just maths.

600kHz is annoyingly too low in some respects, and picosecond jitter is not going to be easy down that close to DC.

[ali_asadzadeh]

As to measuring such things, measure phase noise instead...

Build two of em, lock them in quadrature then a mixer, low pass filter and a low frequency spectrum analyser (Sound card for the close in stuff), turning phase noise into RMS jitter is annoying maths, but it is just maths.

600kHz is annoyingly too low in some respects, and picosecond jitter is not going to be easy down that close to DC.

Thanks for the hints, would you explain more, I did not get it fully.

[Ditiris]

If you're already spending the money on the Si5391 and external PLL, use the Si5391 to generate a clock for a real ADC. Downsample to 600kHz. Doing this with a SAR ADC through the FPGA is asking for trouble. You're not going to get <10ps jitter involving the FPGA in the ADC clocking.

[edigi]

so do we have a way of creating a low speed clock with low jitter?

DDS chip synthesizing sine and creating clock from it with fast comparator like in case of AD9954 (maybe something simpler does it as well)? You don't need to divide anything in FPGA...

[Marco]

Build two of em, lock them in quadrature then a mixer, low pass filter and a low frequency spectrum analyser

Can't you just XOR them? You are kind of committing yourself to pulling a crystal with a varactor at that point though. Which is a lot harder than just taking say a 1.2 MHz crystal oscillator and dividing by 2 with a single discrete flipflop, which you can't pull into quadrature.

Or use a faster oscillator with multiple flipflops for power of 2 or 4 bit presettable counter for non power of 2 divisions, if that helps as edigi suggests. Still, you can't build two and force them into quadrature.

[ejeffrey]

so do we have a way of creating a low speed clock with low jitter?

DDS chip synthesizing sine and creating clock from it with fast comparator like in case of AD9954 (maybe something simpler does it as well)? You don't need to divide anything in FPGA...

That's a good approach for higher frequency but not for 600 kHz.  The slew rate of a 600 kHz sine wave is too low to get the best jitter performance.  A 2V pkpk sine wave only slews about 30 uV in 10 ps.  Noise, drift, and crosstalk on your comparator input all need to be under that to reach 10 ps drift.  That's achievable with careful filtering and component selection but unnecessary trouble.

It's much better to produce a higher frequency square wave -- possibly with a DDS like you describe-- and divide it down.  The square wave has high slew rate regardless of frequency.

You could use a DDS to produce a "square" wave with a controlled rise time followed by a filter and comparator to clean it up but I don't know of any off the shelf DDS chips that do that.